Inventor · disambiguated record
Steven J. Battle
Also filed as: BATTLE STEVEN J
39 granted patents·2 pending applications·40 citations·filing 2015–2022
95Inventor score
Technology areasG06F
Files withIBM41
Top patents by PatentIndex Score
41 records- 0198US11144319B1Redistribution of architected states for a processor register fileIBM·Filed 2020·Granted Oct 12, 2021·19 cites·20 claims
- 0289US11941398B1Fast mapper restore for flush in processorIBM·Filed 2022·Granted Mar 26, 2024·1 cites·20 claims
- 0384US11868773B2Inferring future value for speculative branch resolution in a microprocessorIBM·Filed 2022·Granted Jan 9, 2024·1 cites·20 claims
- 0484US9870045B2Reducing power consumption in a multi-slice computer processorIBM·Filed 2016·Granted Jan 16, 2018·3 cites·7 claims
- 0583US11119772B2Check pointing of accumulator register results in a microprocessorIBM·Filed 2019·Granted Sep 14, 2021·3 cites·18 claims
- 0681US10248426B2Direct register restore mechanism for distributed history buffersIBM·Filed 2016·Granted Apr 2, 2019·3 cites·17 claims
- 0780US10949213B2Logical register recovery within a processorIBM·Filed 2018·Granted Mar 16, 2021·2 cites·20 claims
- 0877US10037259B2Adaptive debug tracing for microprocessorsIBM·Filed 2016·Granted Jul 31, 2018·3 cites·20 claims
- 0973US11995445B2Assignment of microprocessor register tags at issue timeIBM·Filed 2022·Granted May 28, 2024·0 cites·25 claims
- 1072US10379867B2Asynchronous flush and restore of distributed history bufferIBM·Filed 2017·Granted Aug 13, 2019·1 cites·20 claims
- 1171US11163568B2Implementing write ports in register-file array cellIBM·Filed 2018·Granted Nov 2, 2021·1 cites·17 claims
- 1271US11144364B2Supporting speculative microprocessor instruction executionIBM·Filed 2019·Granted Oct 12, 2021·1 cites·18 claims
- 1371US10949205B2Implementation of execution compression of instructions in slice target register file mapperIBM·Filed 2018·Granted Mar 16, 2021·1 cites·20 claims
- 1469US10545765B2Multi-level history buffer for transaction memory in a microprocessorIBM·Filed 2017·Granted Jan 28, 2020·1 cites·20 claims
- 1564US11500642B2Assignment of microprocessor register tags at issue timeIBM·Filed 2020·Granted Nov 15, 2022·0 cites·20 claims
- 1664US11360779B2Logical register recovery within a processorIBM·Filed 2020·Granted Jun 14, 2022·0 cites·20 claims
- 1761US11327757B2Processor providing intelligent management of values buffered in overlaid architected and non-architected register filesIBM·Filed 2020·Granted May 10, 2022·0 cites·20 claims
- 1860US10564691B2Reducing power consumption in a multi-slice computer processorIBM·Filed 2017·Granted Feb 18, 2020·0 cites·14 claims
- 1960US10209757B2Reducing power consumption in a multi-slice computer processorIBM·Filed 2017·Granted Feb 19, 2019·0 cites·7 claims
- 2058US11301254B2Instruction streaming using state migrationIBM·Filed 2019·Granted Apr 12, 2022·0 cites·20 claims
- 2157US11061681B2Instruction streaming using copy select vectorIBM·Filed 2019·Granted Jul 13, 2021·0 cites·20 claims
- 2256US11157276B2Thread-based organization of slice target register file entry in a microprocessor to permit writing scalar or vector data to portions of a single register file entryIBM·Filed 2019·Granted Oct 26, 2021·0 cites·19 claims
- 2356US11093282B2Register file write using pointersIBM·Filed 2019·Granted Aug 17, 2021·0 cites·17 claims
- 2456US10996995B2Saving and restoring a transaction memory stateIBM·Filed 2019·Granted May 4, 2021·0 cites·20 claims
- 2556US9870039B2Reducing power consumption in a multi-slice computer processorIBM·Filed 2015·Granted Jan 16, 2018·0 cites·14 claims
- 2655US11768684B2Compaction of architected registers in a simultaneous multithreading processorIBM·Filed 2020·Granted Sep 26, 2023·0 cites·17 claims
- 2754US11709676B2Inferring future value for speculative branch resolutionIBM·Filed 2021·Granted Jul 25, 2023·0 cites·18 claims
- 2853US10956158B2System and handling of register data in processorsIBM·Filed 2019·Granted Mar 23, 2021·0 cites·15 claims
- 2952US10740140B2Flush-recovery bandwidth in a processorIBM·Filed 2018·Granted Aug 11, 2020·0 cites·20 claims
- 3051US11194578B2Fused overloaded register file read to enable 2-cycle move from condition register instruction in a microprocessorIBM·Filed 2018·Granted Dec 7, 2021·0 cites·18 claims
- 3151US10909034B2Issue queue snooping for asynchronous flush and restore of distributed history bufferIBM·Filed 2017·Granted Feb 2, 2021·0 cites·20 claims
- 3251US10489253B2On-demand GPR ECC error detection and scrubbing for a multi-slice microprocessorIBM·Filed 2017·Granted Nov 26, 2019·0 cites·20 claims
- 3350US11403109B2Steering a history buffer entry to a specific recovery port during speculative flush recovery lookup in a processorIBM·Filed 2018·Granted Aug 2, 2022·0 cites·17 claims
- 3450US11068267B2High bandwidth logical register flush recoveryIBM·Filed 2019·Granted Jul 20, 2021·0 cites·20 claims
- 3549US11561794B2Evicting and restoring information using a single port of a logical register mapper and history buffer in a microprocessor comprising multiple main register file entries mapped to one accumulator register file entryIBM·Filed 2021·Granted Jan 24, 2023·0 cites·20 claims
- 3648US11188332B2System and handling of register data in processorsIBM·Filed 2019·Granted Nov 30, 2021·0 cites·17 claims
- 3747US11030018B2On-demand multi-tiered hang buster for SMT microprocessorIBM·Filed 2017·Granted Jun 8, 2021·0 cites·18 claims
- 3844US10296337B2Preventing premature reads from a general purpose registerIBM·Filed 2016·Granted May 21, 2019·0 cites·17 claims
- 3944US2020019405A1Multiple Level History Buffer for Transaction Memory SupportIBM·Filed 2018·Application pending·0 cites
- 4042US10127121B2Operation of a multi-slice processor implementing adaptive failure state captureIBM·Filed 2016·Granted Nov 13, 2018·0 cites·19 claims
- 4139US2017300336A1Fpscr sticky bit handling for out of order instruction executionIBM·Filed 2016·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →