Inventor

TU YEUR-LUEN

TW246 patents

⚠️ This page may combine multiple inventors who share the name “TU YEUR-LUEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TU YEUR-LUEN

TAIWAN SEMICONDUCTOR MFG CO LTD

Conductive pad structure for hybrid bonding and methods of forming same

Hybrid bonding mechanisms for semiconductor wafers

Dual facing BSI image sensors with wafer level stacking

Deep trench isolation structures and methods of forming same

Bond chuck, methods of bonding, and tool including bond chuck

Buffer layer(s) on a stacked structure having a via

Mechanisms for cleaning substrate surface for hybrid bonding

Deep trench isolation (DTI) structure with a tri-layer passivation layer

Method for alignment, process tool and method for wafer-level alignment

3D integrated circuit and methods of forming the same

Image sensor having improved full well capacity and related method of formation

Method for forming a semiconductor-on-insulator (SOI) substrate

Buffer layer(s) on a stacked structure having a via

SOI substrate, semiconductor device and method for manufacturing the same

Transistor channel

Image sensor scheme for optical and electrical improvement

Image device having multi-layered refractive layer on back surface

Deep trench isolation structure and method of forming same

Transistor channel

Image sensor device and manufacturing method thereof

Stacked capacitor with enhanced capacitance and method of manufacturing the same

Wafer processing method and apparatus

TAIWAN SEMICONDUCTOR MFG

3D integrated circuit and methods of forming the same

Structure of merged vertical capacitor inside spiral conductor for RF and mixed-signal applications

Method of fabricating a metal-insulator-metal (MIM), capacitor structure using a damascene process

Hybrid bonding mechanisms for semiconductor wafers

Method of forming air gap isolation between a bit line contact structure and a capacitor under bit line structure

Structure of merged vertical capacitor inside spiral conductor for RF and mixed-signal applications

Fabrication methods of vertical metal-insulator-metal (MIM) capacitor for advanced embedded DRAM applications

Hybrid bonding and apparatus for performing the same

Capacitor under bitline (CUB) memory cell structure employing air gap void isolation

DRAM capacitor and a method of fabricating the same

Backside illuminated sensor processing

Thin sidewall multi-step HDP deposition method to achieve completely filled high aspect ratio trenches

Method of forming shallow trench isolation with rounded corner and divot-free by using disposable spacer

Methods for forming memory cell structures

Plasmonic nanostructures for organic image sensors

WORLDWIDE SEMICONDUCTOR MANUFA

Method for making dual damascene contact

Method to fabricate DRAM capacitor using damascene processes

Method for making fin-trench structured DRAM capacitor

Method for forming a planar intermetal dielectric layer

VANGUARD INT SEMICONDUCT CORP

Plasma-enhanced chemical vapor deposited SIO2 /SI3 N4 multilayer passivation layer for semiconductor applications

Method for making a plasma-enhanced chemical vapor deposited SiO2 Si3 N4 multilayer passivation layer for semiconductor applications

Method for fabricating a high aspect ratio stacked contact hole

Plasma treatment method for PECVD silicon nitride films for improved passivation layers on semiconductor metal interconnections

TAIWANT SEMICONDUCTOR MFG CO L

Method for forming a self aligned capping layer

WORLDWIDE SEMICONDUCTOR CORP

Process of planarizing crown capacitor for integrated circuit

HSU HUNG-WEN

Sidewall for backside illuminated image sensor metal grid and method of manufacturing same

TIAWAN SEMICONDUCTOR MFG CO LT

Lens structures suitable for use in image sensors and method for making the same

WORLDWIDE SEMICONDUCTOR MFG

Method of forming dual damascene structures