3D integrated circuit and methods of forming the same

Abstract

An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.

What is claimed is: 
     
       1. An integrated circuit structure comprising:
 a first package component comprising:
 a first dielectric layer having a first porosity; 
 a second dielectric layer over and contacting the first dielectric layer, wherein the second dielectric layer is porous and has a second porosity higher than the first porosity; 
 a first bond pad penetrating through the first dielectric layer and the second dielectric layer so that a bottom edge of the bond pad extends at least as far towards a substrate as a bottom edge of the first dielectric layer that is closest to the substrate, wherein the substrate is located fully beneath the first dielectric layer; and 
 a first dielectric barrier layer over and contacting the second dielectric layer, wherein the first bond pad is exposed through the first dielectric barrier layer, the first dielectric barrier layer has a planar top surface, the first bond pad has a second planar top surface higher than a bottom surface of the first dielectric barrier layer and each side edge of the bond pad continuously extends in a straight line from the first dielectric barrier layer to a bottom surface of the first dielectric layer. 
 
 
     
     
       2. The integrated circuit structure of  claim 1  further comprising:
 a second package component bonded to the first package component, wherein the second package component comprises:
 a second bond pad bonded to the first bond pad through metal-to-metal bonding; and 
 a second dielectric barrier layer bonded to the first dielectric barrier layer. 
 
 
     
     
       3. The integrated circuit structure of  claim 1 , wherein the second porosity is between about 5 percent and about 40 percent. 
     
     
       4. The integrated circuit structure of  claim 1 , wherein the second dielectric layer has a dielectric constant smaller than about 3.8. 
     
     
       5. The integrated circuit structure of  claim 1 , wherein the first dielectric barrier layer comprises an inorganic dielectric material. 
     
     
       6. The integrated circuit structure of  claim 1 , wherein the first dielectric barrier layer comprises an organic dielectric material. 
     
     
       7. An integrated circuit structure comprising:
 a first die comprising:
 a top Inter-Metal Dielectric (IMD) comprising a low-k dielectric material; 
 a top metal feature in the top IMD; 
 an etch stop layer overlying the top metal feature and the top IMD; 
 a first dielectric layer over and contacting the etch stop layer; 
 a second dielectric layer over and contacting the first dielectric layer, wherein the second dielectric layer is porous; 
 a first dielectric barrier layer over the second dielectric layer; and 
 a first bond pad extends from a top surface of the first dielectric barrier layer to the top metal feature; and 
 
 a second die comprising:
 a second bond pad bonded to the first bond pad; and 
 a second dielectric barrier layer bonded to the first dielectric barrier layer. 
 
 
     
     
       8. The integrated circuit structure of  claim 7 , wherein the first dielectric layer is formed of Un-doped Silicate Glass (USG) or silicon oxide. 
     
     
       9. The integrated circuit structure of  claim 7 , wherein the second dielectric layer comprises a low-k dielectric material. 
     
     
       10. The integrated circuit structure of  claim 7 , wherein the first dielectric barrier layer comprises silicon oxynitride. 
     
     
       11. The integrated circuit structure of  claim 7 , wherein the first dielectric barrier layer comprises a siloxane-based polymer. 
     
     
       12. The integrated circuit structure of  claim 7 , wherein the first bond pad comprises a conductive barrier layer continuously extending from the top surface of the first dielectric barrier layer to the top metal feature. 
     
     
       13. The integrated circuit structure of  claim 7 , wherein the first bond pad comprises:
 a conductive barrier layer; and 
 a copper-containing material over the conductive barrier layer. 
 
     
     
       14. An integrated circuit structure comprising:
 a first package component comprising:
 an etch stop layer; 
 a first dielectric layer having a first porosity over and contacting the etch stop layer; 
 a second dielectric layer over and contacting the first dielectric layer, wherein the second dielectric layer is porous and has a second porosity higher than the first porosity; 
 a first bond pad penetrating through the first dielectric layer, the second dielectric layer and the etch stop layer; and 
 a first dielectric barrier layer over and contacting the second dielectric layer, wherein the first bond pad is exposed through the first dielectric barrier layer, the first dielectric barrier layer has a planar top surface, and the first bond pad has a second planar top surface higher than a bottom surface of the first dielectric barrier layer; 
 
 a second package component bonded to the first package component, wherein the second package component comprises:
 a second bond pad bonded to the first bond pad through metal-to-metal bonding; and 
 a second dielectric barrier layer bonded to the first dielectric barrier layer. 
 
 
     
     
       15. The integrated circuit structure of  claim 14 , wherein the etch stop layer comprises silicon carbide, silicon nitride or silicon oxynitride. 
     
     
       16. The integrated circuit structure of  claim 14 , wherein the first porosity is lower than about 5 percent. 
     
     
       17. The integrated circuit structure of  claim 14 , wherein the second porosity is between about 5 percent and about 40 percent. 
     
     
       18. The integrated circuit structure of  claim 14 , wherein the porous dielectric layer comprises a low-k dielectric material. 
     
     
       19. The integrated circuit structure of  claim 14 , wherein the first dielectric barrier layer comprises silicon oxynitride.