Inventor

TSAI CHIA-SHIUNG

TW498 patents

⚠️ This page may combine multiple inventors who share the name “TSAI CHIA-SHIUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TSAI CHIA-SHIUNG

TAIWAN SEMICONDUCTOR MFG

3D integrated circuit and methods of forming the same

Methods for hybrid wafer bonding

Organic low K dielectric etch with NH3 chemistry

Structure of merged vertical capacitor inside spiral conductor for RF and mixed-signal applications

High selectivity Si-rich SiON etch-stop layer

Method of fabricating a metal-insulator-metal (MIM), capacitor structure using a damascene process

Method for patterning a polysilicon gate with a thin gate oxide in a polysilicon etcher

RRAM structure and process using composite spacer

Method to improve adhesion between an overlying oxide hard mask and an underlying low dielectric constant material

Fully dry post-via-etch cleaning method for a damascene process

Chemistry for etching organic low-k materials

Method for etching reliable small contact holes with improved profiles for semiconductor integrated circuits using a carbon doped hard mask

Hard mask method for forming chlorine containing plasma etched layer

Method of fabricating a DRAM device featuring alternate fin type capacitor structures

Dual damascene process for carbon-based low-K materials

Plasma etch method for forming residue free fluorine containing plasma etched layers

Method of forming planarized coatings on contact hole patterns of various duty ratios

Dry development process for a bi-layer resist system

Structure of merged vertical capacitor inside spiral conductor for RF and mixed-signal applications

Dual damascene approach for small geometry dimension

High selectivity Si-rich SiON etch-stop layer

Post gate etch cleaning process for self-aligned gate mosfets

Method of dual damascene etching

Method of patterning narrow gate electrode

Method to improve adhesion between low dielectric constant layer and silicon containing dielectric layer

Reactive ion etch method for forming vias through nitrogenated silicon oxide layers

0.3 Micron aperture width patterning process

Method of forming DRAM capacitors with protected outside crown surface for more robust structures

Hybrid bonding and apparatus for performing the same

Isolation trench with a rounded top edge using an etch buffer layer

Resistance variable memory structure and method of forming the same

Methods for fabricating image sensor devices

Capacitor under bitline (CUB) memory cell structure employing air gap void isolation

Post etching treatment process for high density oxide etcher

Plasma etch method for forming patterned chlorine containing plasma etchable silicon containing layer with enhanced sidewall profile uniformity

Method of forming dual damascene structure with improved contact/via edge integrity

Process for forming an integrated contact or via

TAIWAN SEMICONDUCTOR MFG CO LTD

Transfer module for bowed wafers

Air trench in packages incorporating hybrid bonding

Hybrid bonding systems and methods for semiconductor wafers

Hybrid bonding mechanisms for semiconductor wafers

Methods for hybrid wafer bonding integrated with CMOS processing

Dual facing BSI image sensors with wafer level stacking

Oxide film scheme for RRAM structure

Bond chuck, methods of bonding, and tool including bond chuck

RRAM cell with bottom electrode

LIU PING-YIN

Three dimensional integrated circuit structures and hybrid bonding methods for semiconductor wafers

CHEN CHI-MING

Reducing wafer distortion through a low CTE layer

TAIWAN SEMICONDUCTOR MANFACTUR

Method for cleaning silicon wafers with deep trenches

TAIWANT SEMICONDUCTOR MFG CO L

Method for forming a self aligned capping layer