Inventor

KUANG HSUN-CHUNG

TW93 patents

⚠️ This page may combine multiple inventors who share the name “KUANG HSUN-CHUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KUANG HSUN-CHUNG

TAIWAN SEMICONDUCTOR MFG CO LTD

Techniques for MRAM MTJ top electrode connection

Structure and method to expose memory cells with different sizes

Wafer bonding process and structure

3D integrated circuit and methods of forming the same

Integrate rinse module in hybrid bonding platform

Semiconductor structure and method of forming the same

Air trench in packages incorporating hybrid bonding

Particle prevention in wafer edge trimming

Doped sidewall spacer/etch stop layer for memory

Circuit design and layout with high embedded memory density

Threshold voltage-modulated memory device using variable-capacitance and methods of forming the same

FeRAM with laminated ferroelectric film and method forming same

Circuit design and layout with high embedded memory density

Top electrode via with low contact resistance

Resistive memory cell with switching layer comprising one or more dopants

Multi-doped data storage structure configured to improve resistive memory cell performance

Structure and method to expose memory cells with different sizes

MRAM MTJ top electrode connection

Memory device using an etch stop dielectric layer and methods for forming the same

Semiconductor structure

Wafer carrier assembly

Chemical mechanical polishing system and method

Semiconductor structure

Wafer bonding process and structure

3D integrated circuit and methods of forming the same

Techniques to inhibit delamination from flowable gap-fill dielectric

Techniques to inhibit delamination from flowable gap-fill dielectric

Semiconductor device and methods of manufacturing thereof

Capping structure along image sensor element to mitigate damage to active layer

Capping structure along image sensor element to mitigate damage to active layer

Apparatus of chemical mechanical polishing and operating method thereof

Conditioner disk, chemical mechanical polishing device, and method

Circuit design and layout with high embedded memory density

Threshold voltage-modulated memory device using variable-capacitance and methods of forming the same

Integrate rinse module in hybrid bonding platform

Threshold voltage-modulated memory device using variable-capacitance and methods of forming the same

Threshold voltage-modulated memory device using variable-capacitance and methods of forming the same

Integrate rinse module in hybrid bonding platform

Integrate rinse module in hybrid bonding platform

Top electrode via with low contact resistance

Hard mask layer below via structure in display device

Deep trench isolation structure and methods for fabrication thereof

Resistive memory cell with switching layer comprising one or more dopants

FeRAM with laminated ferroelectric film and method forming same

Interface film to mitigate size effect of memory device

Bond pad structure for bonding improvement

Semiconductor device and method of manufacturing the same

Conductive structure connection with interconnect structure

Techniques to inhibit delamination from flowable gap-fill dielectric

TAIWAN SEMICONDUCTOR MFG

3D integrated circuit and methods of forming the same