Inventor · disambiguated record
Bachir Dirahoui
Also filed as: DIRAHOUI BACHIR
10 granted patents·2 pending applications·61 citations·filing 1999–2016
86Inventor score
Top patents by PatentIndex Score
12 records- 0181US8901706B2Thermally stable high-K tetragonal HFO2 layer within high aspect ratio deep trenchesCHUDZIK MICHAEL P·Filed 2012·Granted Dec 2, 2014·4 cites·14 claims
- 0272US7790553B2Methods for forming high performance gates and structures thereofIBM·Filed 2008·Granted Sep 7, 2010·5 cites·14 claims
- 0372US6492259B2Process for making a planar integrated circuit interconnectIBM·Filed 2001·Granted Dec 10, 2002·18 cites·10 claims
- 0471US6800530B2Triple layer hard mask for gate patterning to fabricate scaled CMOS transistorsIBM·Filed 2003·Granted Oct 5, 2004·16 cites·16 claims
- 0568US9496148B1Method of charge controlled patterning during reactive ion etchingIBM·Filed 2015·Granted Nov 15, 2016·1 cites·20 claims
- 0658US9087927B2Thermally stable high-K tetragonal HFO2 layer within high aspect ratio deep trenchesIBM·Filed 2014·Granted Jul 21, 2015·0 cites·18 claims
- 0756US10573526B2Method of charge controlled patterning during reactive ion etchingIBM·Filed 2016·Granted Feb 25, 2020·0 cites·20 claims
- 0853US6281583B1Planar integrated circuit interconnectIBM·Filed 1999·Granted Aug 28, 2001·17 cites·10 claims
- 0951US7358130B2Method for monitoring lateral encroachment of spacer process on a CD SEMIBM·Filed 2006·Granted Apr 15, 2008·0 cites·7 claims
- 1044US7105398B2Method for monitoring lateral encroachment of spacer process on a CD SEMIBM·Filed 2004·Granted Sep 12, 2006·0 cites·11 claims
- 1144US2009256207A1Finfet devices from bulk semiconductor and methods for manufacturing the sameIBM·Filed 2008·Application pending·0 cites
- 1237US2004259303A1Triple layer hard mask for gate patterning to fabricate scaled CMOS transistorsIBM·Filed 2004·Application pending·0 cites
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