Inventor

ABERNATHY CHRISTOPHER M

US29 patents

⚠️ This page may combine multiple inventors who share the name “ABERNATHY CHRISTOPHER M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ABERNATHY CHRISTOPHER M

IBM

Method to reduce power consumption of a register file with multi SMT support

Method and system for restoring register mapper states for an out-of-order microprocessor

Issuing load-dependent instructions in an issue queue in a processing unit of a data processing system

Issue unit for placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline

Bypassing a higher level register file in a processor having a multi-level register file and a set of bypass registers

Efficient usage of a multi-level register file utilizing a register file bypass

Handling data cache misses out-of-order for asynchronous pipelines

Processor livelock recovery by gradual stalling of instruction processing rate during detection of livelock condition

Apparatus and method for handling data cache misses out-of-order for asynchronous pipelines

Placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline

Processor for avoiding reduced performance using instruction metadata to determine not to maintain a mapping of a logical register to a physical register in a first level register file

Thread transition management

Processor for avoiding reduced performance using instruction metadata to determine not to maintain a mapping of a logical register to a physical register in a first level register file

Issuing instructions in-order in an out-of-order processor using false dependencies

Selectively engaging optional data reduction mechanisms for capturing trace data

Method and system for on-demand scratch register renaming

Thread transition management

Thread transition management

Thread transition management

Instruction tracking system for processors

ABERNATHY CHRISTOPHER M

System and method for double-issue instructions using a dependency matrix and a side issue queue

Thread transition management

System and method for double-issue instructions using a dependency matrix

Multi-level register file supporting multiple threads

Issue unit for placing a processor into a gradual slow mode of operation

Tracking deallocated load instructions using a dependence matrix

Multi-level register file supporting multiple threads

Register file supporting transactional processing

Active power dissipation detection based on erroneus clock gating equations