Processor for avoiding reduced performance using instruction metadata to determine not to maintain a mapping of a logical register to a physical register in a first level register file

Abstract

A processor includes a first level register file, second level register file, and register file mapper. The first and second level register files are comprised of physical registers, with the first level register file more efficiently accessed relative to the second level register file. The register file mapper is coupled with the first and second level register files. The register file mapper comprises a mapping structure and register file mapper controller. The mapping structure hosts mappings between logical registers and physical registers of the first level register file. The register file mapper controller determines whether to map a destination logical register of an instruction to a physical register in the first level register file. The register file mapper controller also determines, based on metadata associated with the instruction, whether to write data associated with the destination logical register to one of the physical registers of the second level register file.

What is claimed is: 
     
       1. A method of operating a processor for efficient use of a multi-level register file, the method comprising:
 receiving an indication of a completed instruction, wherein the indication indicates a logical register mapped to a physical register in a first level register file; 
 determining that metadata associated with the completed instruction indicates that maintaining a mapping of the logical register to the physical register in the first level register file and allowing data of the logical register to remain in the physical register in the first level register file will reduce performance of the processor; 
 responsive to said determining that the metadata associated with the completed instruction indicates that maintaining the mapping of the logical register to the physical register in the first level register file and allowing the data of the logical register to remain in the physical register in the first level register file will reduce performance of the processor, writing the data of the logical register to a physical register in a second level register file; 
 determining whether an entry in a mapping structure indicates a mapping between the logical register and the physical register in the first level register file for the completed instruction; 
 indicating in the entry that the entry is to be victimized first if the entry in the mapping structure indicates the mapping between the logical register and the physical register in the first level register file for the completed instruction; and 
 avoiding updating the mapping structure with the mapping between the logical register and the physical register in the first level register file to allow the physical register in the first level register file to be available if the mapping structure does not have an entry indicating the mapping between the logical register and the physical register in the first level register file for the completed instruction. 
 
     
     
       2. The method of  claim 1 ,
 wherein said determining that the metadata associated with the completed instruction indicates that maintaining the mapping of the logical register to the physical register in the first level register file and allowing data of the logical register to remain in the physical register in the first level register file will reduce performance of the processor comprises determining that the metadata associated with the completed instruction indicates that the completed instruction is associated with one of a low priority thread, a microcoded routine, a routine that does not commonly access logical registers, and an excessively thrashing thread. 
 
     
     
       3. The method of  claim 1 ,
 wherein said determining that the metadata associated with the completed instruction indicates that maintaining the mapping of the logical register to the physical register in the first level register file and allowing data of the logical register to remain in the physical register in the first level register file will reduce performance of the processor comprises determining that the metadata associated with the completed instruction indicates that the completed instruction is referencing an infrequently accessed logical register. 
 
     
     
       4. The method of  claim 1 , further comprising:
 incrementing a value in a counter register designated to host the metadata responsive to one of an instruction accessing a logical register and data associated with a thread being written to the second level register file. 
 
     
     
       5. The method of  claim 1 , further comprising:
 resetting a value in a counter register designated to host the metadata responsive to the passage of a set period defined by one of time and clock cycles. 
 
     
     
       6. The method of  claim 1 , further comprising:
 modifying a value in a counter register designated to host the metadata responsive to a program instruction directing the processor to set the metadata to indicate a second value. 
 
     
     
       7. A computer program product for operating a processor for efficient use of a multi-level register file, the computer program product comprising:
 a non-transitory computer readable storage medium having computer usable program code embodied therewith, the computer usable program code configured to:
 receive an indication of a completed instruction, wherein the indication indicates a logical register mapped to a physical register in a first level register file; 
 determine that metadata associated with the completed instruction indicates that maintaining a mapping of the logical register to the physical register in the first level register file and allowing data of the logical register to remain in the physical register in the first level register file will reduce performance of the processor; 
 responsive to a determination that the metadata associated with the completed instruction indicates that maintaining the mapping of the logical register to the physical register in the first level register file and allowing the data of the logical register to remain in the physical register in the first level register file will reduce performance of the processor, write the data of the logical register to a physical register in a second level register file; 
 determine whether an entry in a mapping structure indicates a mapping between the logical register and the physical register in the first level register file for the completed instruction; 
 indicate in the entry that the entry is to be victimized first if the entry in the mapping structure indicates the mapping between the logical register and the physical register in the first level register file for the completed instruction; and 
 avoid updating the mapping structure with the mapping between the logical register and the physical register in the first level register file to allow the physical register in the first level register file to be available if the mapping structure does not have an entry indicating the mapping between the logical register and the physical register in the first level register file for the completed instruction. 
 
 
     
     
       8. The computer program product of  claim 7 ,
 wherein the computer usable program code configured to determine that the metadata associated with the completed instruction indicates that maintaining the mapping of the logical register to the physical register in the first level register file and allowing data of the logical register to remain in the physical register in the first level register file will reduce performance of the processor comprises the computer usable program code configured to determine that the metadata associated with the completed instruction indicates that the completed instruction is associated with one of a low priority thread, a microcoded routine, a routine that does not commonly access logical registers, and an excessively thrashing thread. 
 
     
     
       9. The computer program product of  claim 7 ,
 wherein the computer usable program code configured to determine that the metadata associated with the completed instruction indicates that maintaining the mapping of the logical register to the physical register in the first level register file and allowing data of the logical register to remain in the physical register in the first level register file will reduce performance of the processor comprises the computer usable program code configured to determine that the metadata associated with the completed instruction indicates that the completed instruction is referencing an infrequently accessed logical register. 
 
     
     
       10. The computer program product of  claim 7 , wherein the computer usable program code is further configured to increment a value in a counter register designated to host the metadata responsive to one of an instruction accessing a logical register and data associated with a thread being written to the second level register file. 
     
     
       11. The computer program product of  claim 7 , wherein the computer usable program code is further configured to reset a value in a counter register designated to host the metadata responsive to the passage of a set period defined by one of time and clock cycles. 
     
     
       12. The computer program product of  claim 7 , wherein the computer usable program code is further configured to modify a value in a counter register designated to host the metadata responsive to a program instruction directing the processor to set the metadata to indicate a second value. 
     
     
       13. A processor comprising:
 a first level register file of physical registers; 
 a second level register file of physical registers, wherein the first level register file is more efficiently accessed relative to the second level register file; and 
 a register file mapper coupled with the first level register file and the second level register file, the register file mapper comprising:
 a mapping structure operable to host mappings between logical registers and the physical registers of the first level register file; 
 a register file controller operable to determine, based on metadata associated with an instruction, whether to map a destination logical register of the instruction to one of the physical registers of the first level register file or to write data associated with the destination logical register to one of the physical registers of the second level register file, wherein the register file controller is further operable to update hardware counters responsive to at least one of referencing a logical register and casting out data from the first level register file to a lower level register file; and 
 a register designated to host a value specifying a threshold that represents a high rate of thrashing for a thread. 
 
 
     
     
       14. The processor of  claim 13  further comprising a register designated to host a value specifying a threshold that represents a low frequency accessing of a logical register. 
     
     
       15. The processor of  claim 13 , wherein the register file mapper is operable to determine whether the metadata associated with the instruction indicates at least one of whether the instruction is associated with a low priority thread, the instruction is associated with a microcoded routine, and the instruction is associated with a routine that does not commonly access destination logical registers. 
     
     
       16. The processor of  claim 13  further comprising a register designated to host the metadata. 
     
     
       17. The processor of  claim 13 , wherein the hardware counters are operable to host the metadata.