Inventor · disambiguated record
Christopher M. Abernathy
Also filed as: ABERNATHY CHRISTOPHER M · ABERNATHY CHRISTOPHER MICHAEL
49 granted patents·8 pending applications·479 citations·filing 2001–2019
98Inventor score
Top patents by PatentIndex Score
57 records- 0197US8108655B2Selecting fixed-point instructions to issue on load-store unitABERNATHY CHRISTOPHER MICHAEL·Filed 2009·Granted Jan 31, 2012·148 cites·20 claims
- 0293US8135942B2System and method for double-issue instructions using a dependency matrix and a side issue queueABERNATHY CHRISTOPHER M·Filed 2008·Granted Mar 13, 2012·36 cites·16 claims
- 0393US8046566B2Method to reduce power consumption of a register file with multi SMT supportIBM·Filed 2008·Granted Oct 25, 2011·39 cites·13 claims
- 0492US7689812B2Method and system for restoring register mapper states for an out-of-order microprocessorIBM·Filed 2007·Granted Mar 30, 2010·29 cites·18 claims
- 0592US7350056B2Method and apparatus for issuing instructions from an issue queue in an information handling systemIBM·Filed 2005·Granted Mar 25, 2008·32 cites·17 claims
- 0690US7401242B2Dynamic power management in a processor designIBM·Filed 2005·Granted Jul 15, 2008·22 cites·7 claims
- 0789US8521998B2Instruction tracking system for processorsABERNATHY CHRISTOPHER MICHAEL·Filed 2010·Granted Aug 27, 2013·12 cites·22 claims
- 0887US7313673B2Fine grained multi-thread dispatch block mechanismIBM·Filed 2005·Granted Dec 25, 2007·18 cites·20 claims
- 0986US7437539B2Issue unit for placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipelineIBM·Filed 2006·Granted Oct 14, 2008·13 cites·10 claims
- 1085US7490224B2Time-of-life counter design for handling instruction flushes from a queueIBM·Filed 2005·Granted Feb 10, 2009·13 cites·3 claims
- 1182US8725993B2Thread transition managementABERNATHY CHRISTOPHER M·Filed 2011·Granted May 13, 2014·4 cites·6 claims
- 1282US7681056B2Dynamic power management in a processor designIBM·Filed 2008·Granted Mar 16, 2010·10 cites·7 claims
- 1378US9959121B2Bypassing a higher level register file in a processor having a multi-level register file and a set of bypass registersIBM·Filed 2016·Granted May 1, 2018·2 cites·20 claims
- 1478US7991979B2Issuing load-dependent instructions in an issue queue in a processing unit of a data processing systemIBM·Filed 2008·Granted Aug 2, 2011·9 cites·8 claims
- 1578US7769986B2Method and apparatus for register renamingIBM·Filed 2007·Granted Aug 3, 2010·8 cites·16 claims
- 1678US7434033B2Placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipelineIBM·Filed 2006·Granted Oct 7, 2008·7 cites·11 claims
- 1777US7461239B2Apparatus and method for handling data cache misses out-of-order for asynchronous pipelinesIBM·Filed 2006·Granted Dec 2, 2008·7 cites·23 claims
- 1876US7900024B2Handling data cache misses out-of-order for asynchronous pipelinesIBM·Filed 2008·Granted Mar 1, 2011·6 cites·12 claims
- 1975US9286068B2Efficient usage of a multi-level register file utilizing a register file bypassIBM·Filed 2012·Granted Mar 15, 2016·3 cites·24 claims
- 2075US7890782B2Dynamic power management in an execution unit using pipeline wave flow controlIBM·Filed 2008·Granted Feb 15, 2011·5 cites·12 claims
- 2175US7818544B2Processor livelock recovery by gradual stalling of instruction processing rate during detection of livelock conditionIBM·Filed 2008·Granted Oct 19, 2010·5 cites·20 claims
- 2274US8082423B2Generating a flush vector from a first execution unit directly to every other execution unit of a plurality of execution units in order to block all register updatesABERNATHY CHRISTOPHER MICHAEL·Filed 2005·Granted Dec 20, 2011·7 cites·1 claims
- 2373US8239661B2System and method for double-issue instructions using a dependency matrixABERNATHY CHRISTOPHER M·Filed 2008·Granted Aug 7, 2012·6 cites·20 claims
- 2473US7653848B2Selectively engaging optional data reduction mechanisms for capturing trace dataIBM·Filed 2006·Granted Jan 26, 2010·6 cites·20 claims
- 2570US8200946B2Issue unit for placing a processor into a gradual slow mode of operationABERNATHY CHRISTOPHER M·Filed 2008·Granted Jun 12, 2012·4 cites·20 claims
- 2670US7913070B2Time-of-life counter for handling instruction flushes from a queueIBM·Filed 2008·Granted Mar 22, 2011·4 cites·2 claims
- 2769US8037366B2Issuing instructions in-order in an out-of-order processor using false dependenciesIBM·Filed 2009·Granted Oct 11, 2011·4 cites·17 claims
- 2868US8661227B2Multi-level register file supporting multiple threadsABERNATHY CHRISTOPHER M·Filed 2010·Granted Feb 25, 2014·2 cites·17 claims
- 2967US7328330B2Queue design supporting dependency checking and issue for SIMD instructions within a general purpose processorIBM·Filed 2005·Granted Feb 5, 2008·3 cites·1 claims
- 3066US11256507B2Thread transition managementIBM·Filed 2019·Granted Feb 22, 2022·0 cites·5 claims
- 3166US8099582B2Tracking deallocated load instructions using a dependence matrixABERNATHY CHRISTOPHER M·Filed 2009·Granted Jan 17, 2012·3 cites·20 claims
- 3265US7363469B2Method and system for on-demand scratch register renamingIBM·Filed 2006·Granted Apr 22, 2008·3 cites·7 claims
- 3364US10296339B2Thread transition managementIBM·Filed 2018·Granted May 21, 2019·0 cites·15 claims
- 3464US10275251B2Processor for avoiding reduced performance using instruction metadata to determine not to maintain a mapping of a logical register to a physical register in a first level register fileIBM·Filed 2012·Granted Apr 30, 2019·1 cites·18 claims
- 3564US8028151B2Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelinesIBM·Filed 2008·Granted Sep 27, 2011·2 cites·13 claims
- 3663US8661228B2Multi-level register file supporting multiple threadsABERNATHY CHRISTOPHER M·Filed 2012·Granted Feb 25, 2014·1 cites·8 claims
- 3761US10055226B2Thread transition managementIBM·Filed 2017·Granted Aug 21, 2018·0 cites·10 claims
- 3861US7469357B2Method and apparatus for dynamic power management in an execution unit using pipeline wave flow controlIBM·Filed 2006·Granted Dec 23, 2008·2 cites·6 claims
- 3959US11635961B2Processor for avoiding reduced performance using instruction metadata to determine not to maintain a mapping of a logical register to a physical register in a first level register fileIBM·Filed 2019·Granted Apr 25, 2023·0 cites·17 claims
- 4059US9703561B2Thread transition managementIBM·Filed 2014·Granted Jul 11, 2017·0 cites·20 claims
- 4155US8874880B2Instruction tracking system for processorsIBM·Filed 2013·Granted Oct 28, 2014·0 cites·18 claims
- 4252US7831808B2Queue design system supporting dependency checking and issue for SIMD instructions within a general purpose processorIBM·Filed 2007·Granted Nov 9, 2010·0 cites·12 claims
- 4352US7137013B2Method and apparatus for dynamic power management in an execution unit using pipeline wave flow controlIBM·Filed 2002·Granted Nov 14, 2006·3 cites·10 claims
- 4449US2008127197A1Method and system for on-demand scratch register renamingABERNATHY CHRISTOPHER M·Filed 2008·Application pending·0 cites
- 4548US8020072B2Method and apparatus for correcting data errorsIBM·Filed 2006·Granted Sep 13, 2011·0 cites·8 claims
- 4648US7475232B2Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelinesIBM·Filed 2005·Granted Jan 6, 2009·0 cites·10 claims
- 4746US2009113182A1System and Method for Issuing Load-Dependent Instructions from an Issue Queue in a Processing UnitABERNATHY CHRISTOPHER M·Filed 2007·Application pending·0 cites
- 4846US2008244242A1Using a Register File as Either a Rename Buffer or an Architected Register FileABERNATHY CHRISTOPHER M·Filed 2007·Application pending·0 cites
- 4944US2007118726A1System and method for dynamically selecting storage instruction performance schemeIBM·Filed 2005·Application pending·0 cites
- 5044US2008016408A1System and Method for Streaming High Frequency Trace Data Off-ChipABERNATHY CHRISTOPHER M·Filed 2006·Application pending·0 cites
Showing the top 50 of 57 patent records by PatentIndex Score.
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