Method and system for on-demand scratch register renaming

Abstract

A method and processor for performing on-demand scratch register reallocation by dynamically adjusting the number of scratch registers from within the pool of rename registers includes initially allocating from a set of physical registers one or more architected registers and a pool of one or more rename registers and allocating from the pool of rename registers an initial number of scratch registers for storing microcode operands. In response to detecting that a fetched instruction requires an additional scratch register beyond the initial number, a selected physical register is reallocated from among the pool of rename registers as the additional scratch register, and a flag is set to indicate the rename register is allocated as the additional scratch register. In response to determining that the additional scratch register is no longer needed, the additional scratch register is deallocated and the flag is reset, such that the selected physical register returns to the pool of rename registers.

1 . A processor with reallocation, said processor comprising:
 an instruction-sequencing unit;   an execution unit;   a set of physical registers including one or more architected registers and a pool of multiple rename registers; and   a mapper that allocates from said pool of rename registers an initial number of scratch registers for storing microcode operands, wherein responsive to detecting that a fetched instruction is targeted to a scratch register requiring an additional scratch register beyond said initial number, said mapper reallocates a selected physical register from among said pool of rename registers as said additional scratch register and sets a flag to indicate said rename register is allocated as said additional scratch register, and wherein, responsive to determining that said additional scratch register is no longer needed, deallocating said additional scratch register and resetting said flag, such that said selected physical register returns to said pool of rename registers.   
   
   
       2 . The processor of  claim 8 , wherein said mapper reallocates a selected physical register from among said rename registers as said additional scratch register at a dispatch of said fetched instruction. 
   
   
       3 . The processor of  claim 8 , further comprising an instruction translation unit for detecting said additional scratch register is no longer needed. 
   
   
       4 . The processor of  claim 10 , wherein said instruction translation unit that detects said additional scratch register is no longer needed further comprises means for determining that no unexecuted instructions remain in a thread containing said fetched instruction requiring said additional scratch register. 
   
   
       5 . The processor of  claim 8 , further comprising a single-bit latch. 
   
   
       6 . The processor of  claim 8 , further comprising an instruction translation unit that detects that said fetched instruction requires said additional scratch register beyond said initial number. 
   
   
       7 . The processor of  claim 8 , further comprising means within said mapper for allocating from said pool of rename registers zero scratch registers for storing microcode operands. 
   
   
       8 . A machine-readable medium having a plurality of instructions processable by a machine embodied therein, wherein said plurality of instructions, when processed by said machine, causes said machine to perform a method, comprising:
 initially allocating from a set of physical registers one or more architected registers and a pool of multiple rename registers;   allocating from said pool of rename registers an initial number of scratch registers for storing microcode operands;   in response to detecting that a fetched instruction is targeted to a scratch register requiring an additional scratch register beyond said initial number, reallocating a selected physical register from among said pool of rename registers as said additional scratch register;   setting a flag to indicate said rename register is allocated as said additional scratch register; and   in response to determining that said additional scratch register is no longer needed, deallocating said additional scratch register and resetting said flag, such that said selected physical register returns to said pool of rename registers.   
   
   
       9 . The machine-readable medium of claim  15 , wherein said step of reallocating said selected physical register from among said rename registers as said additional scratch register further comprises reallocating a selected physical register from among said rename registers as said additional scratch register at a dispatch of said fetched instruction. 
   
   
       10 . The machine-readable medium of claim  15 , further wherein said method further comprises determining that said additional scratch register is no longer needed. 
   
   
       11 . The machine-readable medium of claim  15 , wherein said step of determining that said additional scratch register is no longer needed further comprises determining that no unexecuted instructions remain in a thread containing said fetched instruction requiring said additional scratch register. 
   
   
       12 . The machine-readable medium of claim  15 , wherein said step of setting said flag further comprises setting a single-bit latch. 
   
   
       13 . The machine-readable medium of claim  15 , wherein said method further comprises, detecting that said fetched instruction requires said additional scratch register beyond said initial number.