Inventor · disambiguated record
Albert Thomas Williams
Also filed as: WILLIAMS ALBERT T · WILLIAMS ALBERT THOMAS
11 granted patents·1 pending application·252 citations·filing 1997–2009
91Inventor score
Top patents by PatentIndex Score
12 records- 0195US8041928B2Information handling system with real and virtual load/store instruction issue queueIBM·Filed 2008·Granted Oct 18, 2011·46 cites·20 claims
- 0293US7904661B2Data stream prefetching in a microprocessorIBM·Filed 2007·Granted Mar 8, 2011·32 cites·13 claims
- 0392US7290261B2Method and logical apparatus for rename register reallocation in a simultaneous multi-threaded (SMT) processorIBM·Filed 2003·Granted Oct 30, 2007·98 cites·19 claims
- 0490US7350029B2Data stream prefetching in a microprocessorIBM·Filed 2005·Granted Mar 25, 2008·22 cites·7 claims
- 0584US7380066B2Store stream prefetching in a microprocessorIBM·Filed 2005·Granted May 27, 2008·13 cites·7 claims
- 0665US7363469B2Method and system for on-demand scratch register renamingIBM·Filed 2006·Granted Apr 22, 2008·3 cites·7 claims
- 0763US7716427B2Store stream prefetching in a microprocessorIBM·Filed 2008·Granted May 11, 2010·2 cites·11 claims
- 0853US6279144B1Provably correct storage arraysIBM·Filed 1999·Granted Aug 21, 2001·15 cites·10 claims
- 0949US2008127197A1Method and system for on-demand scratch register renamingABERNATHY CHRISTOPHER M·Filed 2008·Application pending·0 cites
- 1048US5995425ADesign of provably correct storage arraysIBM·Filed 1997·Granted Nov 30, 1999·11 cites·7 claims
- 1137US6128722AData processing system having an apparatus for exception tracking during out-of-order operation and method thereforIBM·Filed 1998·Granted Oct 3, 2000·10 cites·38 claims
- 1235US8185371B2Modeling full and half cycle clock variabilityBHANJI ADIL·Filed 2009·Granted May 22, 2012·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →