Inventor · disambiguated record
Mary D. Brown
Also filed as: BROWN MARY D · BROWN MARY DOUGLASS
32 granted patents·6 pending applications·340 citations·filing 2002–2025
96Inventor score
Technology areasG06F
Top patents by PatentIndex Score
38 records- 0197US8108655B2Selecting fixed-point instructions to issue on load-store unitABERNATHY CHRISTOPHER MICHAEL·Filed 2009·Granted Jan 31, 2012·148 cites·20 claims
- 0293US8135942B2System and method for double-issue instructions using a dependency matrix and a side issue queueABERNATHY CHRISTOPHER M·Filed 2008·Granted Mar 13, 2012·36 cites·16 claims
- 0392US8103852B2Information handling system including a processor with a bifurcated issue queueBISHOP JAMES WILSON·Filed 2008·Granted Jan 24, 2012·34 cites·14 claims
- 0492US7689812B2Method and system for restoring register mapper states for an out-of-order microprocessorIBM·Filed 2007·Granted Mar 30, 2010·29 cites·18 claims
- 0591US11487667B1Prediction confirmation for cache subsystemAPPLE INC·Filed 2021·Granted Nov 1, 2022·2 cites·20 claims
- 0689US8380964B2Processor including age tracking of issue queue instructionsIBM·Filed 2009·Granted Feb 19, 2013·18 cites·14 claims
- 0784US10007616B1Methods for core recovery after a cold startAPPLE INC·Filed 2016·Granted Jun 26, 2018·4 cites·20 claims
- 0882US8725993B2Thread transition managementABERNATHY CHRISTOPHER M·Filed 2011·Granted May 13, 2014·4 cites·6 claims
- 0979US8489863B2Processor including age tracking of issue queue instructionsBISHOP JAMES WILSON·Filed 2012·Granted Jul 16, 2013·5 cites·7 claims
- 1078US12481591B2Prediction confirmation for cache subsystemAPPLE INC·Filed 2024·Granted Nov 25, 2025·0 cites·20 claims
- 1178US9959121B2Bypassing a higher level register file in a processor having a multi-level register file and a set of bypass registersIBM·Filed 2016·Granted May 1, 2018·2 cites·20 claims
- 1278US7991979B2Issuing load-dependent instructions in an issue queue in a processing unit of a data processing systemIBM·Filed 2008·Granted Aug 2, 2011·9 cites·8 claims
- 1375US9286068B2Efficient usage of a multi-level register file utilizing a register file bypassIBM·Filed 2012·Granted Mar 15, 2016·3 cites·24 claims
- 1475US8127116B2Dependency matrix with reduced area and power consumptionISLAM SAIFUL·Filed 2009·Granted Feb 28, 2012·10 cites·18 claims
- 1575US2025321744A1Using a Next Fetch Predictor Circuit with Short Branches and Return Fetch GroupsAPPLE INC·Filed 2025·Application pending·0 cites
- 1673US8239661B2System and method for double-issue instructions using a dependency matrixABERNATHY CHRISTOPHER M·Filed 2008·Granted Aug 7, 2012·6 cites·20 claims
- 1772US11880308B2Prediction confirmation for cache subsystemAPPLE INC·Filed 2022·Granted Jan 23, 2024·0 cites·20 claims
- 1870US6988185B2Select-free dynamic instruction schedulingINTEL CORP·Filed 2002·Granted Jan 17, 2006·15 cites·38 claims
- 1969US8037366B2Issuing instructions in-order in an out-of-order processor using false dependenciesIBM·Filed 2009·Granted Oct 11, 2011·4 cites·17 claims
- 2068US8661227B2Multi-level register file supporting multiple threadsABERNATHY CHRISTOPHER M·Filed 2010·Granted Feb 25, 2014·2 cites·17 claims
- 2166US11256507B2Thread transition managementIBM·Filed 2019·Granted Feb 22, 2022·0 cites·5 claims
- 2266US8099582B2Tracking deallocated load instructions using a dependence matrixABERNATHY CHRISTOPHER M·Filed 2009·Granted Jan 17, 2012·3 cites·20 claims
- 2365US12373215B2Using a next fetch predictor circuit with short branches and return fetch groupsAPPLE INC·Filed 2022·Granted Jul 29, 2025·0 cites·20 claims
- 2464US10296339B2Thread transition managementIBM·Filed 2018·Granted May 21, 2019·0 cites·15 claims
- 2564US10275251B2Processor for avoiding reduced performance using instruction metadata to determine not to maintain a mapping of a logical register to a physical register in a first level register fileIBM·Filed 2012·Granted Apr 30, 2019·1 cites·18 claims
- 2664US8086826B2Dependency tracking for enabling successive processor instructions to issueBROWN MARY DOUGLASS·Filed 2009·Granted Dec 27, 2011·4 cites·25 claims
- 2763US8661228B2Multi-level register file supporting multiple threadsABERNATHY CHRISTOPHER M·Filed 2012·Granted Feb 25, 2014·1 cites·8 claims
- 2861US10055226B2Thread transition managementIBM·Filed 2017·Granted Aug 21, 2018·0 cites·10 claims
- 2959US11635961B2Processor for avoiding reduced performance using instruction metadata to determine not to maintain a mapping of a logical register to a physical register in a first level register fileIBM·Filed 2019·Granted Apr 25, 2023·0 cites·17 claims
- 3059US9703561B2Thread transition managementIBM·Filed 2014·Granted Jul 11, 2017·0 cites·20 claims
- 3150US7971161B2Apparatus and method for implementing speculative clock gating of digital logic circuitsIBM·Filed 2008·Granted Jun 28, 2011·0 cites·24 claims
- 3249US2010257339A1Dependency Matrix with Improved PerformanceIBM·Filed 2009·Application pending·0 cites
- 3349US2010257341A1Selective Execution Dependency MatrixIBM·Filed 2009·Application pending·0 cites
- 3449US2010262813A1Detecting and Handling Short Forward Branch Conversion CandidatesIBM·Filed 2009·Application pending·0 cites
- 3548US8078999B2Structure for implementing speculative clock gating of digital logic circuitsBLANER BARTHOLOMEW·Filed 2008·Granted Dec 13, 2011·0 cites·10 claims
- 3646US2009113182A1System and Method for Issuing Load-Dependent Instructions from an Issue Queue in a Processing UnitABERNATHY CHRISTOPHER M·Filed 2007·Application pending·0 cites
- 3744US2014122842A1Efficient usage of a register file mapper mapping structureIBM·Filed 2012·Application pending·0 cites
- 3842US8631223B2Register file supporting transactional processingABERNATHY CHRISTOPHER M·Filed 2010·Granted Jan 14, 2014·0 cites·27 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →