Inventor

DALLABORA MARCO

IT45 patents

⚠️ This page may combine multiple inventors who share the name “DALLABORA MARCO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DALLABORA MARCO

MICRON TECHNOLOGY INC

Data state synchronization

Hybrid memory system interface

Latency-based storage in a hybrid memory system

Latency-based storage in a hybrid memory system

Latency-based storage in a hybrid memory system

Data relocation in hybrid memory

Memory operations on data

Memory management

Program operations in memory

Memory operations on data

Hybrid memory system interface

Memory management

Data state synchronization

Dedicated commands for memory operations

Memory operations on data

Memory management

Data state synchronization

Data state synchronization involving memory cells having an inverted data state written thereto

Latency-based storage in a hybrid memory system

Latency-based storage in a hybrid memory system

Dedicated commands for memory operations

Program operations in memory

Data state synchronization

ST MICROELECTRONICS SRL

Sensing circuitry for reading and verifying the contents of electrically programmable/erasable non-volatile memory cells

Flash EEPROM with on-chip erase source voltage generator

Sensing circuitry for reading and verifying the contents of electrically programmable/erasable non-volatile memory cells

Electrically erasable and programmable non-volatile memory device with testable redundancy circuits

Flash-EEPROM memory array and method for biasing the same

Method of programming a nonvolatile flash-EEPROM memory array using source line switching transistors

Data output stage having feedback loops to precharge the output node

Method of avoiding disturbance during the step of programming and erasing an electrically programmable, semiconductor non-volatile storage device

Method of reading, erasing and programming a nonvolatile flash-EEPROM memory arrray using source line switching transistors

Reference signal generating method and circuit for differential evaluation of the content of nonvolatile memory cells

Nonvolatile flash-EEPROM memory array with source control transistors

Flash EEPROM with on-chip erase source voltage generator

SGS THOMSON MICROELECTRONICS

Method for setting the threshold voltage of a reference memory cell

EEPROM memory with contactless memory cells

Negative charge pump circuit for electrically erasable semiconductor memory devices

Memory cell reading circuit

Method for erasing an electrically programmable and erasable non-volatile memory cell

Generator of reset pulses upon the rise of the power supply for CMOS-type integrated circuits

Reading device for EPROM memory cells with the operational field independent of the threshold jump of the written cells with respect to the virgin cells

Erase voltage control circuit for an electrically erasable non-volatile memory cell

Stacked Charge pump circuit

Sectorized electrically erasable and programmable non-volatile memory device with redundancy