Inventor

HAUSE FRED N

US114 patents

⚠️ This page may combine multiple inventors who share the name “HAUSE FRED N”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HAUSE FRED N

ADVANCED MICRO DEVICES INC

Dissolvable dielectric method

Ultra short trench transistors and process for making same

Substantially planar semiconductor topography using dielectrics and chemical mechanical polish

Integrated circuit having multiple LDD and/or source/drain implant steps to enhance circuit performance

Multi-level transistor fabrication method with high performance drain-to-gate connection

Method of formation of an air gap within a semiconductor dielectric by solvent desorption

CMOS integrated circuit formed by using removable spacers to produce asymmetrical NMOS junctions before asymmetrical PMOS junctions for optimizing thermal diffusivity of dopants implanted therein

Method of making an integrated circuit which uses an etch stop for producing staggered interconnect lines

Nitrogenated trench liner for improved shallow trench isolation

Interlevel dielectric with air gaps to reduce permitivity

Semiconductor fabrication employing a flowable oxide to enhance planarization in a shallow trench isolation process

Interlevel dielectric with air gaps to lessen capacitive coupling

Method of reducing via and contact dimensions beyond photolithography equipment limits

Test structure responsive to electrical signals for determining lithographic misalignment of conductors relative to vias

Integrated circuit having multiple LDD and/or source/drain implant steps to enhance circuit performance

In-line detection and assessment of net charge in PECVD silicon dioxide (oxide) layers

Method for achieving global planarization by forming minimum mesas in large field areas

Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization

Integrated circuit with differing gate oxide thickness and process for making same

Method for forming an integrated circuit having transistors of dissimilarly graded junction profiles

Interlevel dielectric with air gaps to lessen capacitive coupling

Graded MOS transistor junction formed by aligning a sequence of implants to a selectively removable polysilicon sidewall space and oxide thermally grown thereon

Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect

Method of forming low resistance contact structures in vias arranged between two levels of interconnect lines

Integrated circuit with differing gate oxide thickness

Dielectric having an air gap formed between closely spaced interconnect lines

Method and structure for isolating semiconductor devices after transistor formation

Collimated deposition of titanium onto a substantially vertical nitride spacer sidewall to prevent silicide bridging

Method of making a high density interconnect formation

Semiconductor device with layered doped regions and methods of manufacture

Dissolvable dielectric method and structure

Graded MOS transistor junction formed by aligning a sequence of implants to a selectively removable polysilicon sidewall space and oxide thermally grown thereon

Transistor gate conductor having sidewall surfaces upon which a spacer having a profile that substantially prevents silicide bridging is formed

Transistors having a scaled channel length and integrated spacers with enhanced silicidation properties

Semiconductor fabrication employing a spacer metallization technique

Method of planarizing a semiconductor topography using multiple polish pads

Copper-containing plug for connection of semiconductor surface with overlying conductor

Trench isolation structure employing protective sidewall spacers upon exposed surfaces of the isolation trench

Method of making an integrated circuit with oxidizable trench liner

Integrated circuit having local interconnect for reducing signal cross coupled noise

Process of using electrical signals for determining lithographic misalignment of vias relative to electrically active elements

Transistor fabrication employing formation of silicide across source and drain regions prior to formation of the gate conductor

Method of reducing transistor channel length with oxidation inhibiting spacers

Semiconductor trench isolation process resulting in a silicon mesa having enhanced mechanical and electrical properties

MOS transistor employing a removable, dual layer etch stop to protect implant regions from sidewall spacer overetch

Method for forming a highly planarized interlevel dielectric structure

Asymmetrical P-channel transistor having a boron migration barrier and a selectively formed sidewall spacer

Transistor fabrication process employing a common chamber for gate oxide and gate conductor formation

Semiconductor fabrication employing a post-implant anneal within a low temperature high pressure nitrogen ambient to improve channel and gate oxide reliability

ADVANCED MICRO DEVCIES INC

Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect