Transistor fabrication process employing a common chamber for gate oxide and gate conductor formation

Abstract

An integrated circuit transistor is provided having a gate oxide and a gate conductor arranged upon a semiconductor topography, the gate oxide and gate conductor are formed within a common chamber. The initial semiconductor topography includes a silicon substrate having isolation regions disposed within its upper surface. The semiconductor topography may include an defined region, or well, doped opposite the substrate. The semiconductor topography is first placed in the common chamber. A separate chamber is operably placed in gaseous communication with the common chamber. A plasma is created within the separate chamber, causing nitrogen, silicon, and oxygen containing compounds therein to form ions, molecular fragments, and excited molecules which are transported to the common chamber. The ions, molecular fragments, and excited molecules react and bombard the surface of the semiconductor topography to form an oxide layer thereon. The oxide layer is incorporated with nitrogen atoms which act as barrier atoms. Polysilicon is then deposited upon the oxide layer by CVD within the common chamber. The semiconductor topography is never exposed to ambient conditions outside the common chamber during and between the plasma oxide formation and the polysilicon deposition steps. Preventing ingress of outside ambient helps minimize contamination from entering the oxide. During the polysilicon deposition, dopant atoms are forwarded and become entrained within the polysilicon. The barrier atoms within the deposited oxide helps minimize dopant atoms from passing through the oxide and entering the channel below the oxide.

What is claimed is: 
     
       1. A method for forming a transistor, comprising: providing a semiconductor topography having a layer of oxide thereon;   depositing a gate dielectric upon the semiconductor topography and incorporating a plurality of barrier atoms into said gate dielectric concurrent with depositing the gate dielectric;   while maintaining the topography within a common chamber, depositing a layer of polysilicon upon the gate dielectric; and   selectively removing the layer of polysilicon, the layer of oxide and the gate dielectric to form a gate conductor of said transistor, said gate conductor is spaced a dielectric distance by the remaining portions of said gate dielectric incorporating barrier atoms and said layer of oxide above the semiconductor topography.   
     
     
       2. The method as recited in claim 1, wherein said barrier atoms comprise nitrogen. 
     
     
       3. The method as recited in claim 1, further comprising incorporating a plurality of dopants into said polysilicon concurrent with said depositing a layer of polysilicon. 
     
     
       4. The method as recited in claim 3, wherein said dopants comprise arsenic or phosphorous. 
     
     
       5. The method as recited in claim 3, wherein said dopants comprise boron or boron difluoride. 
     
     
       6. The method as recited in claim 1, wherein said semiconductor topography comprises single crystalline silicon. 
     
     
       7. The method as recited in claim 1, wherein said layer of oxide is thermally grown or deposited. 
     
     
       8. The method as recited in claim 1, wherein said common chamber is removed from, but in gaseous communication with, another chamber from which a plasma deposition source is produced. 
     
     
       9. The method as recited in claim 8, wherein said plasma deposition source comprises precipitate material forwarded from said another chamber to said semiconductor topography within said common chamber for producing said gate dielectric followed by said layer of polysilicon. 
     
     
       10. The method as recited in claim 1, wherein said common chamber remains closed during the depositing of said gate dielectric and said polysilicon and during an interim between the depositing of said gate dielectric and said polysilicon. 
     
     
       11. The method as recited in claim 1, wherein said common chamber is maintained at a temperature ranging from approximately 20° C. to approximately 400° C. during said depositing a gate dielectric and said depositing a layer of polysilicon.