Inventor

WANG JOHN JIANSHI

US33 patents

⚠️ This page may combine multiple inventors who share the name “WANG JOHN JIANSHI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WANG JOHN JIANSHI

ADVANCED MICRO DEVICES INC

Method for forming flash memory devices

Elimination of poly cap for easy poly1 contact for NAND product

Method of forming ono stacked films and DCS tungsten silicide gate to improve polycide gate performance for flash memory devices

Effect of doped amorphous Si thickness on better poly 1 contact resistance performance for nand type flash memory devices

High yield performance semiconductor process flow for NAND flash memory products

Self-aligned gate formation using polysilicon polish with peripheral protective layer

Flash memory devices with oxynitride dielectric as the charge storage media

Process to improve the Vss line formation for high density flash memory and related structure associated therewith

Efficient method to detect process induced defects in the gate stack of flash memory devices

Interlevel dielectric thickness monitor for complex semiconductor chips

Test structure to measure interlayer dielectric effects and breakdown and detect metal defects in flash memories

Method for reducing shallow trench isolation edge thinning on tunnel oxides using partial nitride strip and small bird&#39;s beak formation for high performance flash memory devices

Semiconductor isolation material deposition system and method

Memory device having improved programmability

Method and system for eliminating voids in a semiconductor device

Method for reduced gate aspect ratio to improve gap-fill after spacer etch

Semiconductor device with multiple contact sizes

Semiconductor device with multiple contact sizes

Poly I spacer manufacturing process to eliminate polystringers in high density nand-type flash memory devices

In-situ P doped amorphous silicon by NH3 to form oxidation resistant and finer grain floating gates

Method for reducing shallow trench isolation edge thinning on thin gate oxides to improve peripheral transistor reliability and performance for high performance flash memory devices

Method and system for providing contacts with greater tolerance for misalignment in a flash memory

Method of fabricating a shallow trench isolation structure with reduced topography

Flash memory device with monitor structure for monitoring second gate over-etch

Method for monitoring second gate over-etch in a semiconductor device

Elimination of poly cap easy poly 1 contact for NAND product

Method for reduced gate aspect ration to improve gap-fill after spacer etch

Interlevel dielectric thickness monitor for complex semiconductor chips

Method for removing contaminate nitrogen from the peripheral gate region of a non-volatile memory device during production of such device

Manufacturing process to eliminate ONO fence material in high density NAND-type flash memory devices

Method for reducing the step height of shallow trench isolation structures

Method for forming a low barrier height oxide layer on a silicon substrate

ADVANCE MICRO DEVICES INC

Submicron semiconductor device having a self-aligned channel stop region and a method for fabricating the semiconductor device using a trim and etch

Method for reducing shallow trench isolation edge thinning on tunnel oxides using partial nitride strip and small bird's beak formation for high performance flash memory devices