Method for reducing shallow trench isolation edge thinning on thin gate oxides to improve peripheral transistor reliability and performance for high performance flash memory devices

Abstract

A method of semiconductor integrated circuit fabrication. Specifically, one embodiment of the present invention discloses a method for reducing shallow trench isolation (STI) corner recess of silicon in order to reduce STI edge thinning for peripheral thin gate transistor devices 480 in an integrated circuit 400 comprising flash memory devices 380, and both thick 390 and thin 480 gate transistor devices. The method begins by forming a tunnel oxide layer 310 over a semiconductor substrate 430 for the formation of the flash memory devices 380 (step 220 ). A mask 350 is formed over the thin gate transistor devices 480 to inhibit formation of a thick gate oxide layer 360 for the formation of the thick gate transistor devices 390 (step 230 ). The mask 350 reduces shallow trench isolation (STI) recess by eliminating removal of the thick gate oxide layer 360 before forming a thin oxide layer 410 for the thin gate transistor devices 480.

What is claimed is:  
     
       1. A method of semiconductor structure fabrication comprising: 
       a) providing a semiconductor substrate  430  for the formation of an integrated circuit  400  comprising a plurality of memory devices  380 , a plurality of first transistors  390 , and a plurality of second transistors  480  (step  210 );  
       b) forming a tunnel oxide layer  310 , a floating gate layer  320 , and a dielectric layer  330  over said semiconductor substrate  430  for forming said plurality of memory devices  380  (step  220 );  
       c) masking said plurality of second transistors  480  with a mask  350  to inhibit formation of a thick gate oxide layer  360  for said plurality of first transistors  390 , and reduce shallow trench isolation (STI) recess by eliminating removal of said thick gate oxide layer  360  before forming a thin gate oxide layer  410  for said plurality of second transistors  480  (step  230 ).  
     
     
       2. The method of semiconductor structure fabrication as described in  claim 1 , wherein b) further comprises: 
       b1) masking said plurality of memory devices  380  with a second mask  340 ;  
       b2) removing said floating gate layer  320  and said dielectric layer  330  over said plurality of first transistors  390  and said plurality of second transistors  480 ; and  
       b3) removing said second mask  340 .  
     
     
       3. The method of semiconductor structure fabrication as described in  claim 2 , further comprising: 
       creating said mask  350  without removing said second mask  340  by modifying said second mask  340 .  
     
     
       4. The method of semiconductor structure fabrication as described in  claim 1 , wherein c) further comprises: 
       c1) masking said plurality of memory devices  380  with said mask  350 ;  
       c2) removing said tunnel oxide layer  310  over said plurality of first transistors  390 ;  
       c3) removing said mask  350 ; and  
       c4) forming said thick gate oxide layer  360  over said plurality of first transistors  390 .  
     
     
       5. The method of semiconductor structure fabrication as described in  claim 4 , further comprising: 
       d) masking said plurality of first transistors  390  and said memory devices  380  with a second mask  370 ;  
       e) removing said tunnel oxide layer  310  over said plurality of second transistors  480 ;  
       f) removing said second mask  370 ; and  
       g) forming said thin gate oxide layer  410  over said plurality of second transistors  480 .  
     
     
       6. The method of semiconductor structure fabrication as described in  claim 1 , wherein each of said plurality of memory devices  380  is a flash memory device. 
     
     
       7. The method of semiconductor structure fabrication as described in  claim 1 , wherein each of said plurality of first transistors  390  is a thick gate oxide transistor for high voltage operation. 
     
     
       8. The method of semiconductor structure fabrication as described in  claim 1 , wherein each of said plurality of second transistors  480  is a thin gate oxide transistor for low voltage operation. 
     
     
       9. A method of semiconductor structure fabrication comprising: 
       a) forming a tunnel oxide layer  310 , a floating gate layer  320 , and a dielectric layer  330  over a semiconductor substrate  430  for a first transistor  390 , a second transistor  480 , and a memory device  380  (step  520 ;  
       b) forming said memory device  380  having said tunnel oxide layer  310 , said floating gate layer  320 , and said dielectric layer  330  (step  530 );  
       c) masking said second transistor  480  with a mask  350  to inhibit formation of a thick gate oxide layer  360  and to reduce shallow trench isolation (STI) recess associated with removing said thick gate oxide layer  360  (step  540 );  
       d) forming said thick gate oxide layer  360  for said first transistor  390  (step  550 ); and  
       e) forming a thin gate oxide layer  410  for said second transistor  480  with reduced STI recess (step  560 ), wherein e) further comprises:  
       e1) masking said first transistor  390  and said memory device  380  with a second mask  370 ;  
       e2) removing said tunnel oxide layer  310 ;  
       e3) removing said second mask  370 ; and  
       e4) forming said thin gate oxide layer  410  over said second transistor  480 .  
     
     
       10. The method of semiconductor structure fabrication as described in  claim 9 , wherein b) comprises: 
       b1) masking said memory device  380  with a second mask  340 ;  
       b2) removing said floating gate layer  320  and said dielectric layer  330  over said first  390  and second  480  transistors; and  
       b3) removing said second mask  340 .  
     
     
       11. The method of semiconductor structure fabrication as described in  claim 10 , wherein c) further comprises: 
       creating said mask  350  without removing said second mask  340  by modifying said second mask  340 .  
     
     
       12. The method of semiconductor structure fabrication as described in  claim 9 , wherein d) comprises: 
       d1) masking said memory device  380  with said mask  350 ;  
       d2) removing said tunnel oxide layer  310  over said first transistor  390 ;  
       d3) removing said mask  350 ; and  
       d4) forming said thick gate oxide layer  360  over said first transistor  390 .  
     
     
       13. The method of semiconductor structure fabrication as described in  claim 9 , wherein said memory device  380  is a flash memory device, said first transistor  390  is a thick gate transistor, and said second transistor  480  is a thin gate transistor. 
     
     
       14. The method of semiconductor structure fabrication as described in  claim 9 , further comprising: 
       separating said first transistor  390 , said second transistor  480 , and said memory device  380  with a plurality of STI regions  490 , said separating performed before a) (step  510 ).  
     
     
       15. A method of semiconductor structure fabrication comprising: 
       a) separating a memory device  380 , a first transistor  380 , and a second transistor  480  with a plurality of shallow trench isolation (STI) regions  490  (step  510 );  
       b) forming a tunnel oxide layer  310  for an integrated circuit  400  comprising said memory device  380 , said first transistor  390 , and said second transistor  480  (step  520 ); and  
       c) reducing STI recess in said second transistor  480  by masking said second transistor  480  having said tunnel oxide layer  310  with a mask  350  to inhibit formation of a thick gate oxide layer  360  for said first transistor  390  to eliminate removal of said thick gate oxide layer  360  before forming a thin gate oxide layer  410  for said second transistor  480  (step  540 ).  
     
     
       16. The method of semiconductor structure fabrication as described in  claim 15 , wherein b) further comprises: 
       b1) forming a floating gate layer  320  and a dielectric layer  330  over said tunnel oxide layer  310  (step  520 );  
       b2) masking said memory device  380  with a second mask  340 ;  
       b3) removing said floating gate layer  320  and said dielectric layer  330  over said tunnel oxide layer  310  over said first  390  and second transistor  480 ; and  
       b4) removing said second mask  340 , wherein said b1) through b4) are performed before c).  
     
     
       17. The method of semiconductor structure fabrication as described in  claim 15 , wherein c) further comprises: 
       c1) masking said memory device  380  with said mask  350  (step  550 );  
       c2) removing said tunnel oxide layer  310  over said first transistor  390  (step  550 );  
       c3) removing said mask  350  (step  550 ); and  
       c4) forming said thick gate oxide layer  360  over said first transistor  390  (step  550 ).  
     
     
       18. The method of semiconductor structure fabrication as described in  claim 17 , further comprising: 
       d) masking said first transistor  390  and said memory device  380  with a second mask  370  (step  560 );  
       e) removing said tunnel oxide layer  310  over said second transistor  480  (step  560 );  
       f) removing said second mask  370  (step  560 ); and  
       g) forming said thin gate oxide layer  410  over said second transistor  480  (step  560 ).  
     
     
       19. The method of semiconductor structure fabrication as described in  claim 15 , wherein a thickness of said thin gate oxide layer  410  is less than 35 Angstroms. 
     
     
       20. The method of semiconductor structure fabrication as described in  claim 15 , wherein said memory device  380  is a flash memory device, said first transistor  390  is a thick gate oxide transistor, and said second transistor  480  is a thin gate oxide transistor. 
     
     
       21. A method of semiconductor structure fabrication comprising: 
       a) providing a semiconductor substrate  430  for the formation of an integrated circuit  400  comprising a plurality of memory devices  380 , a plurality of first transistors  390 , and a plurality of second transistors  480  (step  210 );  
       b) forming a tunnel oxide layer  310 , a floating gate layer  320 , and a dielectric layer  330  over said semiconductor substrate  430  for forming said plurality of memory devices  380  (step  220 );  
       c) masking said plurality of second transistors  480  with a mask  350  to inhibit formation of a thick gate oxide layer  360  for said plurality of first transistors  390 , and reduce shallow trench isolation (STI) recess by eliminating removal of said thick gate oxide layer  360  before forming a thin gate oxide layer  410  for said plurality of second transistors  480  (step  230 ), wherein c) further comprises:  
       c1) masking said plurality of memory devices  380  with said mask  350 ;  
       c2) removing said tunnel oxide layer  310  over said plurality of first transistors  390 ;  
       c3) removing said mask  350 ; and  
       c4) forming said thick gate oxide layer  360  over said plurality of first transistors  390 ;  
       d) masking said plurality of first transistors  390  and said memory devices  380  with a second mask  370 ;  
       e) removing said tunnel oxide layer  310  over said plurality of second transistors  480 ;  
       f) removing said second mask  370 ; and  
       g) forming said thin gate oxide layer  410  over said plurality of second transistors  480 .  
     
     
       22. A method of semiconductor structure fabrication comprising: 
       a) separating a memory device  380 , a first transistor  380 , and a second transistor  480  with a plurality of shallow trench isolation (STI) regions  490  (step  510 );  
       b) forming a tunnel oxide layer  310  for an integrated circuit  400  comprising said memory device  380 , said first transistor  390 , and said second transistor  480  (step  520 ); and  
       c) reducing STI recess in said second transistor  480  by masking said second transistor  480  having said tunnel oxide layer  310  with a mask  350  to inhibit formation of a thick gate oxide layer  360  for said first transistor  390  to eliminate removal of said thick gate oxide layer  360  before forming a thin gate oxide layer  410  for said second transistor  480  (step  540 ), wherein c) further comprises:  
       c1) masking said memory device  380  with said mask  350  (step  550 );  
       c2) removing said tunnel oxide layer  310  over said first transistor  390  (step  550 );  
       c3) removing said mask  350  (step  550 ); and  
       c4) forming said thick gate oxide layer  360  over said first transistor  390  (step  550 );  
       d) masking said first transistor  390  and said memory device  380  with a second mask  370  (step  560 );  
       e) removing said tunnel oxide layer  310  over said second transistor  480  (step  560 );  
       f) removing said second mask  370  (step  560 ); and  
       g) forming said thin gate oxide layer  410  over said second transistor  480  (step  560 ).