Inventor

BRAUN GEORG

DE59 patents

⚠️ This page may combine multiple inventors who share the name “BRAUN GEORG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BRAUN GEORG

INFINEON TECHNOLOGIES AG

Configuration for data transmission in a semiconductor memory system, and relevant data transmission method

Method for calibrating semiconductor devices using a common calibration reference and a calibration circuit

Semiconductor memory and method for adapting the phase relationship between a clock signal and strobe signal during the acceptance of write data to be transmitted

System for determining a reference level and evaluating a signal on the basis of the reference level

Memory module and method for operating a memory module in a data memory system

Semiconductor memory configuration with a refresh logic circuit, and method of refreshing a memory content of the semiconductor memory configuration

Integrated memory having a differential sense amplifier

Semiconductor memory array with serial control/address bus

Memory with a temperature sensor, dynamic memory and memory with a clock unit and method of sensing a temperature of a memory

Buffer chip and method for controlling one or more memory arrangements

Data processing system having configurable components

Method and circuit for allocating memory arrangement addresses

Circuit configuration for generating a reference voltage for reading a ferroelectric memory

Ferroelectric memory configuration

Electronic circuit with a driver circuit

Ferroelectric transistor and method for fabricating it

Charge pump with charge equalization for improved efficiency

Method for fabricating a ferroelectric memory configuration

Transmitting data into a memory cell array

Method for combining logic-based circuit units and memory-based circuit units and circuit arrangement

Operating method for an integrated memory having writeable memory cells and corresponding integrated memory

Integrated memory with plate line segments

Integrated memory having memory cells and reference cells, and operating method for such a memory

Semiconductor circuit configuration

Integrated memory having memory cells and reference cells, and corresponding operating method

Circuit configuration for reading a memory cell having a ferroelectric capacitor

Ferroelectric memory array composed of a multiplicity of memory cells each having at least one selection transistor and one storage capacitor driven via word lines and bit lines

Method for writing and reading a ferroelectric memory

Buffer component for a memory module, and a memory module and a memory system having such buffer component

Ferroelectric read/write memory with series-connected memory cells (CFRAM)

Monolithically integrable inductor

Integrated memory and corresponding operating method

Decoder element for generating an output signal having three different potentials and an operating method for the decoder element

Electronic circuit for a method for storing information, said circuit comprising ferroelectric flip-flops

Memory configuration and method for reading a state from and storing a state in a ferroelectric transistor

Integrated memory with redundancy and method for repairing an integrated memory

Integrated circuit

Method for determining the optimum access strategy

Integrated memory with redundancy

Integrated circuit memory with low resistance, segmented power supply lines

QIMONDA AG

Memory dies for flexible use and method for configuring memory dies

Bus termination system and method

High speed memory architecture

Apparatus and method for switching an apparatus to a power saving mode

Horizontal dual in-line memory modules

Memory chip with settable termination resistance circuit

Integrated semiconductor memory with determination of a chip temperature

Command protocol for integrated circuits

SIEMENS AG

Ferroelectric memory and method for preventing aging in a memory cell

Implantation mask for producing a memory cell configuration