Ferroelectric memory and method for preventing aging in a memory cell

Abstract

An integrated memory includes a cell array having bit lines, word lines and writable memory cells. A first differential sense amplifier has connections connected to a data line pair through which the first sense amplifier reads information from one of the memory cells during a read access operation in order to amplify it subsequently, and through which the first sense amplifier writes information to one of the memory cells during a write access operation. The relevant information is transferred as differential signals through the data line pair and is temporarily stored by the first sense amplifier during every write access operation. The memory also has a switching unit through which the data line pair is connected to the connections of the first sense amplifier, for interchanging the lines of the data line pair in relation to the connections of the first sense amplifier, depending on the switching state of the switching unit. The switching state of the switching unit is changed at least once during a write access operation, so that the information to be written is written to the relevant memory cell by the first sense amplifier initially in noninverted form and then in inverted form. A method for preventing aging in a memory cell in an integrated memory is also provided.

We claim: 
     
       1. An integrated memory, comprising: a cell array having bit lines and word lines;   writable memory cells disposed in said cell array;   a data line pair;   a first differential sense amplifier having connections connected to said data line pair, said first differential sense amplifier reading information from one of said memory cells over said data line pair during a read access operation in order to amplify the information subsequently, and said first sense amplifier writing information to one of said memory cells over said data line pair during a write access operation, said data line pair transferring the information as differential signals, and said first sense amplifier temporarily storing the information during every write access operation;   a switching unit having a switching state, said switching unit connecting said data line pair to said connections of said first sense amplifier, for interchanging lines of said data line pair in relation to said connections of said first sense amplifier depending on said switching state of said switching unit; and   said switching state of said switching unit changing at least once during said write access operation, so that the information to be written is written to a relevant one of said memory cells by said first sense amplifier initially in noninverted form and then in inverted form.   
     
     
       2. The integrated memory according to claim 1, wherein said switching state of said switching unit does not change during said write access operation in a first operating mode, and said switching state of said switching unit changes at least once during said write access operation in a second operating mode. 
     
     
       3. The integrated memory according to claim 1, wherein said data line pair is formed from a pair of said bit lines, and said first sense amplifier is a primary sense amplifier connected directly to said bit line pair. 
     
     
       4. The integrated memory according to claim 1, wherein: said first sense amplifier is a secondary sense amplifier; and   at least two second sense amplifiers are primary sense amplifiers, said primary sense amplifiers are connected through at least one respective pair of said bit lines to said memory cells, and said primary sense amplifiers are connected through said data line pair to said first sense amplifier.   
     
     
       5. The integrated memory according to claim 2, wherein said memory cells have a storage capability decreasing as a function of a number of at least one of write and read access operations being performed, said first operating mode is a normal operating mode and said second operating mode is an operating mode preventing aging. 
     
     
       6. The integrated memory according to claim 5, wherein said memory cells are ferroelectric memory cells. 
     
     
       7. The integrated memory according to claim 6, wherein: said memory cells have a ferroelectric storage capacitor for storing information; and   a voltage drop across said storage capacitor during said write access operation to a respective one of said memory cells is higher in said second operating mode than in said first operating mode.   
     
     
       8. A method for preventing aging in a memory cell of an integrated memory according to claim 1, which comprises: reading and temporarily storing information stored in said memory cell in said first sense amplifier;   writing the information temporarily stored in said sense amplifier back to said memory cell at least twice; and   changing said switching state of said switching unit after each time the information is written back.