Inventor

HATAKENAKA MAKOTO

JP29 patents

⚠️ This page may combine multiple inventors who share the name “HATAKENAKA MAKOTO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HATAKENAKA MAKOTO

MITSUBISHI ELECTRIC CORP

Multi-bank semiconductor memory device suitable for integration with logic

Semiconductor integrated circuit device with large internal bus width, including memory and logic circuit

Semiconductor integrated circuit device comprising synchronous DRAM core and logic circuit integrated into a single chip and method of testing the synchronous DRAM core

Semiconductor integrated circuit device allowing accurate evaluation of access time of memory core contained therein and access time evaluating method

Semiconductor memory device capable of block writing in large bus width

Phase-locked circuit and interated circuit device

Synchronized clock generating apparatus

Synchronizing pulse generating circuit

Semiconductor device downsizing its built-in driver

Period measuring device

Semiconductor integrated circuit including a capacitor and a fuse element

Semiconductor memory device

Synchronized clock generating apparatus

Line delay generator using one-port RAM

RENESAS TECH CORP

Memory circuit

Semiconductor integrated circuit for multi-chip package with means to optimize internal drive capacity

Semiconductor integrated circuit device comprising RAM with command decode system and logic circuit integrated into a single chip and testing method of the RAM with command decode system

Method of testing a semiconductor memory device

Information device including main processing circuit, interface circuit, and microcomputer

IIX INC

Unevenness correction data generation device

Panel drive circuit

Input signal correction device

Input signal correction device

Unevenness correction system, unevenness correction apparatus and panel drive circuit

MITSUBISHI ELEC SYS LSI DESIGN

Semiconductor memory device having improved bit line structure

Test circuit

Field effect transistor array including doped two-cell isolation region for preventing latchup

MISUBISHI DENKI KABUSHIKI KAIS

Variable delay circuit for varying delay time and pulse width

RENESAS ELECTRONICS CORP

Information device including main processing circuit, interface circuit, and microcomputer