P

Inventor

HUI ANGELA

US47 patents
⚠️ This page may combine multiple inventors who share the name “HUI ANGELA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ADVANCED MICRO DEVICES INC

18 patents
US6573172B1Jun 3, 2003

Methods for improving carrier mobility of PMOS and NMOS devices

ADVANCED MICRO DEVICES INC395 citations99
US5635423AJun 3, 1997

Simplified dual damascene process for multi-level metallization and interconnection structure

ADVANCED MICRO DEVICES INC374 citations99
US6706576B1Mar 16, 2004

Laser thermal annealing of silicon nitride for increased density and etch selectivity

ADVANCED MICRO DEVICES INC79 citations98
US6509232B1Jan 21, 2003

Formation of STI (shallow trench isolation) structures within core and periphery areas of flash memory device

ADVANCED MICRO DEVICES INC65 citations96
US5907781AMay 25, 1999

Process for fabricating an integrated circuit with a self-aligned contact

ADVANCED MICRO DEVICES INC59 citations96
US6236091B1May 22, 2001

Method of forming a local interconnect with improved etch selectivity of silicon dioxide/silicide

ADVANCED MICRO DEVICES INC24 citations93
US6765254B1Jul 20, 2004

Structure and method for preventing UV radiation damage and increasing data retention in memory cells

ADVANCED MICRO DEVICES INC30 citations92
US6642148B1Nov 4, 2003

RELACS shrink method applied for single print resist mask for LDD or buried bitline implants using chemically amplified DUV type photoresist

ADVANCED MICRO DEVICES INC46 citations92
US6465303B1Oct 15, 2002

Method of manufacturing spacer etch mask for silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile memory

ADVANCED MICRO DEVICES INC22 citations92
US6461951B1Oct 8, 2002

Method of forming a sidewall spacer to prevent gouging of device junctions during interlayer dielectric etching including silicide growth over gate spacers

ADVANCED MICRO DEVICES INC37 citations92
US6391729B1May 21, 2002

Shallow trench isolation formation to eliminate poly stringer with controlled step height and corner rounding

ADVANCED MICRO DEVICES INC23 citations92
US6483153B1Nov 19, 2002

Method to improve LDD corner control with an in-situ film for local interconnect processing

ADVANCED MICRO DEVICES INC15 citations84
US6573140B1Jun 3, 2003

Process for making a dual bit memory device with isolated polysilicon floating gates

ADVANCED MICRO DEVICES INC11 citations74
US6764929B1Jul 20, 2004

Method and system for providing a contact hole in a semiconductor device

ADVANCED MICRO DEVICES INC2 citations63
US6713809B1Mar 30, 2004

Dual bit memory device with isolated polysilicon floating gates

ADVANCED MICRO DEVICES INC2 citations63
US6444530B1Sep 3, 2002

Process for fabricating an integrated circuit with a self-aligned contact

ADVANCED MICRO DEVICES INC2 citations63
US6605517B1Aug 12, 2003

Method for minimizing nitride residue on a silicon wafer

ADVANCED MICRO DEVICES INC2 citations62
US7023046B2Apr 4, 2006

Undoped oxide liner/BPSG for improved data retention

ADVANCED MICRO DEVICES INC3 citations60

SPANSION LLC

16 patents
US6894342B1May 17, 2005

Structure and method for preventing UV radiation damage in a memory cell and improving contact CD control

SPANSION LLC18 citations84
US6833581B1Dec 21, 2004

Structure and method for preventing process-induced UV radiation damage in a memory cell

SPANSION LLC13 citations84
US8035153B2Oct 11, 2011

Self-aligned patterning method by using non-conformal film and etch for flash memory and other semiconductor applications

SPANSION LLC9 citations83
US8022468B1Sep 20, 2011

Ultraviolet radiation blocking interlayer dielectric

SPANSION LLC7 citations83
US7696038B1Apr 13, 2010

Methods for fabricating flash memory devices

SPANSION LLC4 citations63
US7732276B2Jun 8, 2010

Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications

SPANSION LLC4 citations62
US7691751B2Apr 6, 2010

Selective silicide formation using resist etchback

SPANSION LLC2 citations62
US6974995B1Dec 13, 2005

Method and system for forming dual gate structures in a nonvolatile memory using a protective layer

SPANSION LLC3 citations62
US7951675B2May 31, 2011

SI trench between bitline HDP for BVDSS improvement

SPANSION LLC3 citations61
US7622389B1Nov 24, 2009

Selective contact formation using masking and resist patterning techniques

SPANSION LLC2 citations60
US8384146B2Feb 26, 2013

Methods for forming a memory cell having a top oxide spacer

SPANSION LLC0 citations52
US8012830B2Sep 6, 2011

ORO and ORPRO with bit line trench to suppress transport program disturb

SPANSION LLC0 citations52
US7067388B1Jun 27, 2006

Flash memory device and method of forming the same with improved gate breakdown and endurance

SPANSION LLC1 citations52
US7906807B2Mar 15, 2011

Use of a polymer spacer and Si trench in a bitline junction of a flash memory cell to improve TPD characteristics

SPANSION LLC0 citations51
US7776688B2Aug 17, 2010

Use of a polymer spacer and Si trench in a bitline junction of a flash memory cell to improve TPD characteristics

SPANSION LLC0 citations51
US7785965B2Aug 31, 2010

Dual storage node memory devices and methods for fabricating the same

SPANSION LLC0 citations50

CHENG NING

2 patents

CYPRESS SEMICONDUCTOR CORP

2 patents

KINOSHITA HIROYUKI

2 patents

FANG SHENQING

2 patents

FASL LLC

1 patent

(unassigned)

1 patent

FASL LLP

1 patent

HUI ANGELA

1 patent

MIN KYUNGHOON

1 patent