Method for fabricating a memory device having reverse LDD

Abstract

A method for fabricating a semiconductor device. Specifically, a method that includes forming a source and drain region in a periphery transistor, exhibiting a channel width between the source and drain regions suitable for operation at predetermined voltages. After forming the source and drain regions, to eliminate diffusion of lightly doped drain regions resulting from a later formation of the source and drain regions, forming the lightly doped drain regions adjacent to the source and drain regions of the periphery transistor. After forming the lightly doped drain regions in the periphery transistor, the method includes forming a source region and a drain region in a core memory cell, independent of forming the source and drain regions in the periphery transistor.

1. A reverse LDD method for fabricating a semiconductor device, comprising:
 a) providing a substrate having a periphery transistor region and a core memory cell region; 
 b) forming a first source region and a first drain region in said substrate of said periphery transistor region exhibiting a channel width between said first source region and said first drain region; 
 c) forming lightly doped drain (LDD) regions adjacent to said first source region and said first drain region in said periphery transistor region; 
 d) concurrently with said forming LDD regions, forming a second source region and a second drain region in said core memory cell region; and 
 e) depositing a sidewall spacer over said LDD regions of said periphery transistor region, and said second source and drain regions of said core memory cell region; and 
 f) limiting formation of said sidewall spacer to allow space for the formation of a drain contact to said second drain region said core memory cell region, thereby isolating said formation of said drain contact to said second source region of said core memory cell region. 
 
     
     
       2. The method as recited in  claim 1  wherein said forming a first source region and a first drain region further comprises:
 b1) depositing a silicon oxide liner over said periphery transistor region and core memory cell region, wherein a periphery transistor in said periphery transistor region comprises a gate oxide layer formed on a semiconductor substrate between said first source region and said first drain region, and a polysilicon layer that is disposed on top of said gate oxide layer; and 
 b2) depositing a silicon nitride layer disposed on top of said silicon oxide liner; and 
 b3) forming said sidewall spacer wide enough to form said channel width between said first source region and said first drain region. 
 
     
     
       3. The method as recited in  claim 2  wherein said depositing a silicon nitride layer further comprises:
 wherein said silicon nitride layer fills regions between core memory cells in said core memory cell region preventing formation of said second source region and said second drain region. 
 
     
     
       4. The method as recited in  claim 1  wherein a core memory cell in said core memory cell region is a flash memory cell comprising:
 a tunnel oxide layer formed on a semiconductor substrate between said second source and said second drain regions; 
 a floating gate formed on said tunnel oxide layer; 
 a multi-level insulating layer formed on said floating gate; and 
 a control gate formed on said insulating layer. 
 
     
     
       5. The method as recited in  claim 2  wherein said forming a second source region and a second drain region comprises:
 removing said silicon nitride layer; 
 forming said LDD regions in said periphery transistor region; 
 concurrently forming said second source region and said second drain region; and 
 activating said second source and said second drain regions by performing a first rapid thermal anneal cycle. 
 
     
     
       6. The method as recited in  claim 5  wherein said second source and drain regions are exposed to a single RTA cycle. 
     
     
       7. The method as recited in  claim 1  wherein said forming said first source region and said first drain region further comprises:
 depositing a silicon oxide liner over said periphery transistor, on top of which is deposited a layer of silicon nitride, said layer of silicon nitride along with said silicon oxide liner forming a two-layer liner; 
 depositing a silicon oxide layer disposed on top of said two-layer liner; and 
 forming said sidewall spacer with sufficient width to form said channel width between said first source region and said first drain region. 
 
     
     
       8. The method as recited in  claim 7  further comprising:
 performing a rapid thermal anneal cycle; and 
 removing said sidewall spacer. 
 
     
     
       9. A method for fabricating a source, drain and LDD in a semiconductor device, comprising:
 a) depositing a silicon oxide liner across a plurality of periphery transistors and a plurality of core memory cells formed on a substrate; 
 b) depositing a silicon nitride layer across said silicon oxide liner to form first sidewall spacers on said plurality of periphery transistors, wherein said silicon nitride layer fills regions between core memory cells in said plurality of core memory cells preventing formation of second source regions and said second drain regions in said plurality of core memory cells; 
 c) doping first source regions and first drain regions in said plurality of periphery transistors prior to performing a lightly doped drain implant; 
 d) removing said first sidewall spacers; 
 e) performing said lightly doped drain LDD implant in said plurality of periphery transistors to form LDD regions in said plurality of periphery transistors; 
 f) concurrently with said performing said LDD implant, doping said second source regions and said second drain regions in said plurality of core memory cells; 
 g) performing a minimum number of rapid thermal anneal cycles; and 
 h) depositing a layer of silicon nitride to form a second sidewall spacer over said LDD regions of said plurality of periphery transistors, said second source and drain regions of said plurality of core memory cells, wherein formation of said second sidewall spacer is limited to allow space for the formation of drain contacts to at least one of said second drain regions of said plurality of periphery transistors, thereby isolating said formation of said drain contact to said second source region of said plurality of core memory cells. 
 
     
     
       10. The method as described in  claim 9  wherein said plurality of core memory cells are flash memory cells comprising:
 a tunnel oxide layer formed on a semiconductor substrate between said second source and drain regions; 
 a floating gate formed on said tunnel oxide layer; 
 a multi-level insulating layer formed on said floating gate; and 
 a control gate formed on said insulating layer. 
 
     
     
       11. A method for fabricating a semiconductor device, comprising:
 a) depositing a two-layer liner comprised of a first layer of silicon oxide topped with silicon nitride across the surface of said semiconductor device, said two-layer liner covered by a second layer of silicon oxide; 
 b) forming a sidewall spacer for a periphery transistor said sidewall spacer fills regions around a core memory cell preventing formation of a second source region and a second drain region in said core memory cell; 
 c) forming a first source region and a first drain region in said periphery transistor exhibiting a channel width between said first source and drain regions; 
 d) removing said sidewall spacer and forming lightly doped drain (LDD) regions adjacent to said first source and drain regions; and 
 e) concurrently with said forming LDD regions, forming said second source region and said second drain region in said core memory cell; 
 f) depositing another layer of silicon nitride to form a second sidewall spacer over said LDD regions of said periphery transistor, said second source and drain regions of said core memory cell, wherein formation of said second sidewall spacer is limited to allow space for the formation of a drain contact to said second drain region of said periphery transistor, thereby isolating said formation of said drain contact to said second source region of said plurality of core memory cell. 
 
     
     
       12. The method as recited in  claim 11  wherein said silicon nitride of said a) is for the purpose of protecting said layer of silicon oxide during said removing. 
     
     
       13. The method as recited in  claim 11  wherein said core memory cell is a flash memory cell comprising:
 a tunnel oxide layer formed on a semiconductor substrate between said second source and drain regions; 
 a floating gate formed on said tunnel oxide layer; 
 a multi-level insulating layer formed on said floating gate; and 
 a control gate formed on said insulating layer. 
 
     
     
       14. The method as recited in  claim 11  wherein said e) comprises:
 activating said second source and drain regions by performing a first rapid thermal anneal (RTA) cycle. 
 
     
     
       15. The method as recited in  claim 14  wherein said second source and drain regions are exposed to a single RTA cycle. 
     
     
       16. The method as recited in  claim 11  wherein said forming said second source region and said second drain region comprises:
 e1) forming a common source coupled to said second source region.