Inventor

KUMAR MAHENDER

US24 patents

⚠️ This page may combine multiple inventors who share the name “KUMAR MAHENDER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KUMAR MAHENDER

IBM

STI formation in semiconductor device including SOI and bulk silicon regions

Metal gate MOSFET by full semiconductor metal alloy conversion

Dual metal gate finFETs with single or dual high-K gate dielectric

Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof

Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness for low-substrate bias operation

Transistor with recessed cross couple for gate contact over active region integration

Structure and method for manufacturing device with ultra thin SOI at the tip of a V-shape channel

Method of fabricating a vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness

Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness for low-substrate bias operation

Field effect device including inverted V shaped channel region and method for fabrication thereof

Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof

Structures, fabrication methods, design structures for strained fin field effect transistors (FinFets)

Methods for forming high performance gates and structures thereof

Ultra-thin SOI vertical bipolar transistors with an inversion collector on thin-buried oxide (BOX) for low substrate-bias operation and methods thereof

STI formation in semiconductor device including SOI and bulk silicon regions

Method and structure for forming multiple self-aligned gate stacks for logic devices

EDRAM including metal plates

Method for deep trench etching through a buried insulator layer

GLOBALFOUNDRIES INC

Methods of forming vertical field effect transistors with self-aligned contacts and the resulting structures

Methods to control fin tip placement

Threshold voltage and well implantation method for semiconductor devices

Integrated circuit products with gate structures positioned above elevated isolation structures

ANGYAL MATTHEW S

Pedestal guard ring having continuous M1 metal barrier connected to crack stop

GAUTHIER JR ROBERT J

Self-protected electrostatic discharge field effect transistor (SPESDFET), an integrated circuit incorporating the SPESDFET as an input/output (I/O) pad driver and associated methods of forming the SPESDFET and the integrated circuit