Method and structure for forming multiple self-aligned gate stacks for logic devices

Abstract

A method for forming multiple self-aligned gate stacks, the method comprising, forming a first group of gate stack layers on a first portion of a substrate, forming a second group of gate stack layers on a second portion of the substrate adjacent to the first portion of the substrate, etching to form a trench disposed between the first portion and the second portion of the substrate, and filling the trench with an insulating material.

1. A method for forming multiple self-aligned gate stacks, the method comprising sequentially:
 forming a lower portion of a first group of gate stack layers on a first portion of a substrate by:
 forming a first layer of gate dielectric on a substrate; 
 depositing a first electrode layer on the first layer of gate dielectric; 
 depositing a first sacrificial layer of material on the first electrode layer; 
 depositing a first hardmask layer on the first sacrificial layer of material; 
 developing a block level lithography feature on the first hardmask layer to partially define a first gate stack area: and 
 etching to removing a portion of the first hardmask layer, the first sacrificial layer, and the first electrode layer; 
 
 forming a lower portion of a second group of gate stack layers on a second portion of the substrate adjacent to the first portion of the substrate by:
 depositing a second electrode layer on the first layer of gate dielectric and the first hardmask layer; 
 depositing a second sacrificial layer on the second electrode layer; 
 depositing a second hardmask layer on the second sacrificial layer; 
 developing a block level lithography feature on the second hardmask layer to partially define a second gate stack area; and 
 etching to removing a portion of the second hardmask layer, the second sacrificial layer, and the second electrode layer; 
 
 etching to form a trench disposed between the first portion and the second portion of the substrate; 
 filling the trench with an insulating material, 
 forming a conductive layer on the first and second electrode layers and the trench; and 
 patterning the conductive layer so as to form the first and second groups of gate stack layers.