Inventor
HARTSWICK THOMAS J
US16 patents
Patents
16 patentsUS5034348AJul 23, 1991
Process for forming refractory metal silicide layers of different thicknesses in an integrated circuit
IBM129 citations97
US5420455AMay 30, 1995
Array fuse damage protection devices and fabrication method
IBM49 citations95
US5523253AJun 4, 1996
Array protection devices and fabrication method
IBM28 citations92
US6627926B2Sep 30, 2003
Method of designing and structure for visual and electrical test of semiconductor devices
IBM16 citations91
US6274393B1Aug 14, 2001
Method for measuring submicron images
IBM17 citations83
US5926738AJul 20, 1999
Interconnects using metal spacers and method for forming same
IBM7 citations74
US5808364ASep 15, 1998
Interconnects using metal spacers
IBM15 citations74
US10438803B2Oct 8, 2019
Semiconductor structures having low resistance paths throughout a wafer
IBM1 citations73
US10177000B2Jan 8, 2019
Semiconductor structures having low resistance paths throughout a wafer
IBM1 citations73
US9620371B2Apr 11, 2017
Semiconductor structures having low resistance paths throughout a wafer
IBM3 citations73
US5907763AMay 25, 1999
Method and device to monitor integrated temperature in a heat cycle process
IBM8 citations73
US6251773B1Jun 26, 2001
Method of designing and structure for visual and electrical test of semiconductor devices
IBM5 citations72
US9691623B2Jun 27, 2017
Semiconductor structures having low resistance paths throughout a wafer
IBM0 citations52
US9478427B2Oct 25, 2016
Semiconductor structures having low resistance paths throughout a wafer
IBM0 citations52
US9312140B2Apr 12, 2016
Semiconductor structures having low resistance paths throughout a wafer
IBM0 citations52
US10134670B2Nov 20, 2018
Wafer with plated wires and method of fabricating same
IBM0 citations41