Inventor

LINDER BARRY P

US55 patents

⚠️ This page may combine multiple inventors who share the name “LINDER BARRY P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LINDER BARRY P

IBM

Metal gate CMOS with at least a single gate metal and dual gate dielectrics

Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices

Low threshold voltage semiconductor device with dual threshold voltage control means

Reducing dark current in germanium photodiodes by electrical over-stress

Reducing dark current in germanium photodiodes by electrical over-stress

Monitoring aging of silicon in an integrated circuit device

Bulk finFET with super steep retrograde well

Managing aging of silicon in an integrated circuit device

High performance CMOS circuits, and methods for fabricating same

Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devices

Low threshold voltage semiconductor device with dual threshold voltage control means

Metal gate CMOS with at least a single gate metal and dual gate dielectrics

Method of fabricating a metal gate CMOS with at least a single gate metal and dual gate dielectrics

Metal gates with low charge trapping and enhanced dielectric reliability characteristics for high-k gate dielectric stacks

Bulk finFET with super steep retrograde well

BTI degradation test circuit

Analytics to determine customer satisfaction

Reducing dark current in germanium photodiodes by electrical over-stress

Test circuit to isolate HCI degradation

On-chip leakage measurement

Hydroxyl group termination for nucleation of a dielectric metallic oxide

Method to improve reliability of high-K metal gate stacks

Determining appropriateness of sampling integrated circuit test data in the presence of manufacturing variations

Three plate MIM capacitor via integrity verification

Non-destructive analysis to determine use history of processor

Circuit to detect previous use of computer chips using passive test wires

Measuring individual device degradation in CMOS circuits

Analytics to determine customer satisfaction

Measuring individual device degradation in CMOS circuits

Reduction of negative bias temperature instability

Multi-plasma nitridation process for a gate dielectric

Dynamic predictor of semiconductor lifetime limits

Reduction of negative bias temperature instability

Reducing dark current in germanium photodiodes by electrical over-stress

Touch movement activation for gaining access beyond a restricted access gateway

Reducing dark current in germanium photodiodes by electrical over-stress

Reducing dark current in germanium photodiodes by electrical over-stress

Reduction of negative bias temperature instability

Measurement for transistor output characteristics with and without self heating

Selective thickening of pFET dielectric

Touch movement activation for gaining access beyond a restricted access gateway

Hydroxyl group termination for nucleation of a dielectric metallic oxide

Measurement for transistor output characteristics with and without self heating

Method to improve reliability of high-K metal gate stacks

Selective thickening of PFET dielectric

Selective thickening of pFET dielectric

GLOBALFOUNDRIES INC

Multi-plasma nitridation process for a gate dielectric

Multi-plasma nitridation process for a gate dielectric

ANDO TAKASHI

Structure and method to form input/output devices

DORIS BRUCE B

Metal gate CMOS with at least a single gate metal and dual gate dielectrics