Structure and method to form input/output devices

Abstract

A limited number of cycles of atomic layer deposition (ALD) of Hi-K material followed by deposition of an interlayer dielectric and application of further Hi-K material and optional but preferred annealing provides increased Hi-K material content and increased breakdown voltage for input/output (I/O) transistors compared with logic transistors formed on the same chip or wafer while providing scalability of the inversion layer of the I/O and logic transistors without significantly compromising performance or bias temperature instability (BTI) parameters.

We claim: 
     
       1. A field effect transistor including
 a gate dielectric stack interposed between a gate electrode and a semiconductor conduction channel, said gate dielectric stack comprising
 a layer of oxide material, and 
 a composite layer of a volume of interlayer material intermixed with a volume of Hi-K material wherein said volume of Hi-K material is comprised of respective volumes of two layers of Hi-K material, said respective volumes of Hi-K material being formed from predetermined numbers of ALD layers of Hi-K material in respective layers of said two layers of Hi-K material, and 
 
 wherein said composite layer has a graded concentration of nitrogen diffused from said volume of interlayer material between said two layers of Hi-K material. 
 
     
     
       2. A field effect transistor as recited in  claim 1  wherein Hi-K material in said composite layer is formed from a volume of Hi-K material deposited by a number of ALD cycles of Hi-K material in a first layer and a number of ALD Hi-K cycles in a second layer, said first layer and said second layer being separated by said interlayer material. 
     
     
       3. A field effect transistor as recited in  claim 2  wherein said number of cycles of ALD Hi-K in said first layer is in a range of five to ten and said number of cycles of ALD Hi-K in said second layer is in a range of twenty-two to twenty-six. 
     
     
       4. A field effect transistor as recited in  claim 1  wherein said layer of oxide material comprises a number of monolayers of ALD silicon oxide and nitrogen wherein said number of monolayers is in a range of eleven to fifteen. 
     
     
       5. A field effect transistor as recited in  claim 1  wherein said composite layer comprises a substantially homogeneous mixture of interlayer material and Hi-K material. 
     
     
       6. A field effect transistor as recited in  claim 1  further including
 a passivation layer interposed between said conduction channel and said layer of oxide material. 
 
     
     
       7. A field effect transistor as recited in  claim 1 , wherein said conduction channel includes germanium or silicon. 
     
     
       8. An integrated circuit comprising
 a plurality of logic transistors, and 
 a plurality of I/O transistors, wherein at least one said I/O transistor includes a gate dielectric stack interposed between a gate electrode and a conduction channel, said gate dielectric stack comprising
 a layer of oxide material, and 
 a composite layer of a volume of interlayer material and a volume of Hi-K material wherein said volume of Hi-K material in a logic transistor is comprised of a volume of a layer of Hi-K material and said volume of Hi-K material in an I/O transistor is comprised of respective volumes of two layers of Hi-K material, and 
 
 wherein said composite layer has a graded concentration of nitrogen diffused from said volume of interlayer material between said two layers of Hi-K material. 
 
     
     
       9. An integrated circuit as recited in  claim 8  wherein Hi-K material in said composite layer is formed from a volume of Hi-K material deposited by first a number of ALD cycles of Hi-K material in a first layer and a second number of ALD cycles of Hi-K material in a second layer, said first layer and said second layer being separated by the interlayer material. 
     
     
       10. An integrated circuit as recited in  claim 9 , wherein said plurality of logic transistors include a composite layer comprising a substantially homogeneous mixture of Hi-K material and interlayer material and wherein a volume of Hi-K material in said composite layer of said plurality of I/O transistors exceeds a volume of Hi-K material in said composite layer of said logic transistors by an amount of Hi-K material in said first layer of composite material. 
     
     
       11. An integrated circuit as recited in  claim 9  wherein said first number of cycles of ALD Hi-K in said first layer is in a range of five to ten and said second number of cycles of ALD Hi-K in said second layer is in the range of twenty-two to twenty-six. 
     
     
       12. An integrated circuit as recited in  claim 8  wherein said composite layer comprises a substantially homogeneous mixture of the interlayer material and Hi-K material. 
     
     
       13. An integrated circuit as recited in  claim 8  further including
 a passivation layer interposed between said conduction channel and said layer of oxide material. 
 
     
     
       14. An integrated circuit as recited in  claim 8  wherein said layer of oxide material is a volume of oxynitride material deposited by a number of cycles of ALD silicon oxide and nitrogen wherein said number of cycles is in the range of eleven to fifteen. 
     
     
       15. An integrated circuit as recited in  claim 8 , wherein said conduction channel includes germanium or silicon. 
     
     
       16. A method of manufacture of an integrated circuit comprising logic transistors and I/O transistors, said method comprising steps of
 forming an oxynitride layer at an I/O transistor location and a logic transistor location, 
 forming a layer of Hi-K material at said I/O transistor location, 
 forming an interlayer dielectric layer at said I/O transistor location and at logic transistor locations, 
 depositing a layer of Hi-K material on said interlayer dielectric layer, and 
 causing intermixing of said Hi-K material and material of said interlayer dielectric layer, 
 whereby volume of Hi-K at said I/O transistor locations differs from volume of Hi-K material at said logic transistor locations. 
 
     
     
       17. A method as recited in  claim 16  including the further step of
 removing said Hi-K material from sites of logic transistors prior to said step of forming said interlayer dielectric layer. 
 
     
     
       18. A method as recited in  claim 17  including a further step of
 annealing said Hi-K material and said interlayer dielectric layer to cause intermixing of said Hi-K material layer and said interlayer dielectric layer. 
 
     
     
       19. A method as recited in  claim 16  including a further step of
 annealing said Hi-K material and said interlayer dielectric layer to cause intermixing of said Hi-K material and said interlayer dielectric layer. 
 
     
     
       20. A method as recited in  claim 16 , including a further step of
 forming a passivation layer on semiconductor material at a location of a transistor channel prior to said step of forming an oxynitride layer.