Inventor

CHIU GORDON RAYMOND

CA56 patents

⚠️ This page may combine multiple inventors who share the name “CHIU GORDON RAYMOND”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHIU GORDON RAYMOND

ALTERA CORP

Method and apparatus for performing physical synthesis hill-climbing on multi-processor machines

Method and apparatus for implementing layers on a convolutional neural network accelerator

Register retiming and verification of an integrated circuit design

Method and apparatus for performing timing closure analysis when performing register retiming

Method and apparatus for performing timing closure analysis when performing register retiming

Memory interface circuitry with data strobe signal sharing capabilities

Method and apparatus for performing multiple stage physical synthesis

Method and apparatus for performing multiple stage physical synthesis

Method and apparatus for designing and implementing a convolution neural net accelerator

Integrated circuits having input-output circuits with dedicated memory controller circuitry

Method and apparatus for performing register retiming in the presence of false path timing analysis exceptions

Circuits and methods for DQS autogating

Circuits and methods for DQS autogating

Configuring a device to debug systems in real-time

Speculative circuit design component graphical user interface

Timing analysis with end-of-life pessimism removal

Method and apparatus for performing post-placement routability optimization

Method and apparatus for implementing user-guided speculative register retiming in a compilation flow

Retiming programmable devices incorporating random access memories

Incremental register retiming of an integrated circuit design

Method and apparatus for performing register retiming in the presence of timing analysis exceptions

Incremental register retiming of an integrated circuit design

Method and apparatus for performing register retiming in the presence of timing analysis exceptions

Method and apparatus for relocating design modules while preserving timing closure

System and methods for adjusting memory command placement

Methods and systems for improving a maximum operating frequency of a PLD having a shift register within an embedded memory block

Retiming programmable devices incorporating random access memories

Method and apparatus for implementing layers on a convolutional neural network accelerator

Method and apparatus for relocating design modules while preserving timing closure

Techniques for compiling and generating a performance analysis for an integrated circuit design

Method and apparatus for performing multiple stage physical synthesis

Methods and apparatus for probing signals from a circuit after register retiming

Method and apparatus for implementing periphery devices on a programmable circuit using partial reconfiguration

Method and apparatus for implementing periphery devices on a programmable circuit using partial reconfiguration

Supporting pseudo open drain input/output standards in a programmable logic device

Supporting pseudo open drain input/output standards in a programmable logic device

Programmable device configuration methods incorporating retiming

CHIU GORDON RAYMOND

M/A for performing automatic latency optimization on system designs for implementation on programmable hardware

Method and apparatus for performing simultaneous register retiming and combinational resynthesis during physical synthesis

Methods and systems for measuring and presenting performance data of a memory controller system

Hierarchical arbitration

Systems and methods for using memory commands

Area-efficient dynamically-configurable memory controller

FENDER JOSHUA DAVID

Gating and sampling a data strobe signal using a shared enable signal

Low frequency variation calibration circuitry

SINGH DESHANAND

Method and apparatus for performing multiple stage physical synthesis

MANOHARARAJAH VALAVAN

Method and apparatus for performing look up table unpacking and repacking for resynthesis

BLUNNO IVAN

Systems and methods for memory interface calibration

GAMSA BENJAMIN

Method and apparatus for automatically configuring memory size

WONG JASON

Method and apparatus for optimizing implementation of a soft processor executing a fixed program on a target device