Retiming programmable devices incorporating random access memories

Abstract

A method of retiming a circuit that includes a RAM having data stored therein, a register following the RAM, and registers preceding the RAM for registering input, address and enable signals of the RAM includes pushing a value in the register following the RAM back into a memory location in the RAM, pushing back data stored in the RAM and initial values in the registers preceding the RAM to accommodate the value pushed back from the register following the RAM, and setting new values in the registers preceding the RAM so that, on a first clock cycle after retiming, the circuit assumes a condition before retiming. The method also may be used to configure a programmable logic device with a user logic design.

What is claimed is: 
     
       1. A method of configuring an integrated circuit device with a user logic design incorporating an initialized random-access memory (“RAM”), said method comprising:
 identifying initialization conditions of said RAM and an output register thereof; 
 retiming said RAM by: 
 pushing initialization values of input, address and enable registers of said RAM backward through said integrated circuit device, and pushing an initialization value of said output register to a memory location in said RAM, and 
 setting new values of said input, address and enable registers so that starting from those new values, said RAM will achieve said initialization conditions after one clock cycle; 
 incorporating said initialization values and said new values into a configuration for said integrated circuit device; and 
 applying said configuration to said integrated circuit device. 
 
     
     
       2. The method of  claim 1  wherein:
 said integrated circuit device is a programmable integrated circuit device; 
 said incorporating comprises incorporating said initialization values and said new values into a configuration bitstream for said programmable integrated circuit device; and 
 said applying comprises storing said configuration bitstream in memory of said programmable integrated circuit device. 
 
     
     
       3. The method of  claim 1  wherein:
 said RAM is a dual-port RAM; and 
 said setting new values comprises setting both a read address and a write address to said memory location in said RAM. 
 
     
     
       4. The method of  claim 1  wherein:
 said RAM is a single-port RAM that allows, at one address, simultaneous writing of a new value and reading of an old value; and 
 said setting new values comprises setting an address to said memory location in said RAM. 
 
     
     
       5. The method of  claim 1  wherein:
 said setting new values comprises setting said input register to a retimed value determined by said identifying to be an initialization condition of said memory location. 
 
     
     
       6. The method of  claim 5  wherein:
 said initialization value of said enable register disables writing to said RAM; 
 said setting new values comprises setting a new value of said enable register to enable writing to said RAM; and 
 after said one clock cycle, said RAM is configured as a read-only memory with said retimed value from said input register written into said memory location. 
 
     
     
       7. A programmable integrated circuit device configured in accordance with the method of  claim 1 . 
     
     
       8. A non-transitory machine readable storage medium encoded with instructions for performing a method of configuring an integrated circuit device with a user logic design incorporating an initialized random-access memory (“RAM”), said instructions comprising:
 instructions to identify initialization conditions of said RAM and an output register thereof; 
 instructions to retime said RAM, including: 
 instructions to push initialization values of input, address and enable registers of said RAM backward through said integrated circuit device, and to push an initialization value of said output register to a memory location in said RAM, and 
 instructions to set new values of said input, address and enable registers so that starting from those new values, said RAM will achieve said initialization conditions after one clock cycle; 
 instructions to incorporate said initialization values and said new values into a configuration for said integrated circuit device; and 
 instructions to apply said configuration to said integrated circuit device. 
 
     
     
       9. The non-transitory machine readable storage medium of  claim 8  wherein:
 said integrated circuit device is a programmable integrated circuit device; 
 said instructions to incorporate comprise instructions to incorporate said initialization values and said new values into a configuration bitstream for said programmable integrated circuit device; and 
 said instructions to apply comprise instructions to store said configuration bitstream in memory of said programmable integrated circuit device. 
 
     
     
       10. The non-transitory machine readable storage medium of  claim 8  wherein:
 said RAM is a dual-port RAM; and 
 said instructions to set new values comprise instructions to set both a read address and a write address to said memory location in said RAM. 
 
     
     
       11. The non-transitory machine readable storage medium of  claim 8  wherein:
 said RAM is a single-port RAM that allows, at one address, simultaneous writing of a new value and reading of an old value; and 
 said instructions to set new values comprise instructions to set an address to said memory location in said RAM. 
 
     
     
       12. The non-transitory machine readable storage medium of  claim 8  wherein:
 said instructions to set new values comprise instructions to set said input register to a retimed value determined by execution of said instructions to identify to be an initialization condition of said memory location. 
 
     
     
       13. The non-transitory machine readable storage medium of  claim 12  wherein:
 said initialization value of said enable register disables writing to said RAM; 
 said instructions to set new values comprise instruction to set a new value of said enable register to enable writing to said RAM; whereby: 
 after said one clock cycle, said RAM is configured as a read-only memory with said retimed value from said input register written into said memory location. 
 
     
     
       14. A method of retiming a circuit that includes a random-access memory (“RAM”) having data stored therein, a register following said RAM, and registers preceding said RAM for registering input, address and enable signals of said RAM, said method comprising:
 pushing a value in said register following said RAM back into a memory location in said RAM; 
 pushing back data stored in said RAM and initial values in said registers preceding said RAM to accommodate said value pushed back from said register following said RAM; and 
 setting new values in said registers preceding said RAM so that, on a first clock cycle after retiming, said circuit assumes a condition before retiming. 
 
     
     
       15. The method of  claim 14  further comprising, prior to said pushing a value, determining said condition. 
     
     
       16. The method of  claim 14  wherein said circuit is a programmable integrated circuit device, said method further comprising:
 incorporating said value in said register following said RAM, said data stored in said RAM, said initial values in said registers preceding said RAM, and said new values, into a configuration for said programmable integrated circuit device; and 
 applying said configuration to said programmable integrated circuit device. 
 
     
     
       17. The method of  claim 16  wherein
 said incorporating comprises incorporating said value in said register following said RAM, said data stored in said RAM, said initial values in said registers preceding said RAM, and said new values into a configuration bitstream for said programmable integrated circuit device; and 
 said applying comprises storing said configuration bitstream in memory of said programmable integrated circuit device. 
 
     
     
       18. The method of  claim 14  wherein:
 said RAM is a dual-port RAM; and 
 said setting new values comprises setting both a read address and a write address to said memory location in said RAM. 
 
     
     
       19. The method of  claim 14  wherein:
 said RAM is a single-port RAM that allows, at one address, simultaneous writing of a new value and reading of an old value; and 
 said setting new values comprises setting an address to said memory location in said RAM. 
 
     
     
       20. The method of  claim 14  wherein:
 an initialization value of said enable signal in a register preceding said RAM disables writing to said RAM; 
 said setting new values comprises setting a new value of said enable register to enable writing to said RAM, said enable signal that disables writing being pushed further back; and 
 after said first clock cycle, said enable signal that disables writing is written back to said enable register so that said RAM is configured as a read-only memory, and said value pushed back from said register following said RAM is written back into said memory location.