Inventor

BRYANT ANDRES

US182 patents

⚠️ This page may combine multiple inventors who share the name “BRYANT ANDRES”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BRYANT ANDRES

IBM

CMOS back-gated keeper technique

Transistor structure with thick recessed source/drain structures and fabrication process of same

FinFET SRAM cell with chevron FinFET logic

Fin-type field effect transistor structure with merged source/drain silicide and method of forming the structure

Fin-type field effect transistor structure with merged source/drain silicide and method of forming the structure

Double gated transistor and method of fabrication

Strained-silicon CMOS device and method

FinFET with low gate capacitance and low extrinsic resistance

High-voltage high-speed SOI MOSFET

Methods for forming decoupling capacitors

Backgated FinFET having different oxide thicknesses

Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs

Grounded body SOI SRAM cell

SOI pass-gate disturb solution

Method and structures for dual depth oxygen layers in silicon-on-insulator processes

Device method for enhanced avalanche SOI CMOS

SOI pass-gate disturb solution

Device design for enhanced avalanche SOI CMOS

Self-aligned gate sidewall spacer in a corrugated FET

Self-aligned gate sidewall spacer in a corrugated FET and method of making same

Asymmetric multi-gate finFET

Merged fin structures for finFET devices

Air-gap insulated interconnections

Integrated circuit having pairs of parallel complementary FinFETs

Finfet/trigate stress-memorization method

Air-gap insulated interconnections

Disposable spacer for symmetric and asymmetric Schottky contact to SOI mosfet

Hybrid orientation field effect transistors (FETs)

Double-Gate FETs (field effect transistors)

Fin capacitor

Integrated circuit having pairs of parallel complementary FinFETs

Fin-based double poly dynamic threshold CMOS FET with spacer gate and method of fabrication

Matched transistors and methods for forming the same

Method and structure for creating high density buried contact for use with SOI processes for high performance logic

SOI low capacitance body contact

Disposable spacer for symmetric and asymmetric Schottky contact to SOI MOSFET

Self-aligned dynamic threshold CMOS device

SOI MOSFET body contact and method of fabrication

Self-aligned dynamic threshold CMOS device

Double gated transistor and method of fabrication

Double gated vertical transistor with different first and second gate materials

Body contact MOSFET

Method and structures for dual depth oxygen layers in silicon-on-insulator processes

Body contact MOSFET

ANDERSON BRENT A

Integrated circuit and a method using integrated process steps to form deep trench isolation structures and deep trench capacitor structures for the integrated circuit

Maskless inter-well deep trench isolation structure and methods of manufacture

GLOBALFOUNDRIES US 2 LLC

Method of forming a complementary metal oxide semiconductor structure with N-type and P-type field effect transistors having symmetric source/drain junctions and optional dual silicides

ADKISSON JAMES W

Low lag transfer gate device

BASKER VEERARAGHAVAN S

Method for fabricating finFET with merged fins and vertical silicide

BRYANT ANDRES

Integrated circuit device with series-connected field effect transistors and integrated voltage equalization and method of forming the device