Device design for enhanced avalanche SOI CMOS

Abstract

A device design for an FET in SOI CMOS which is designed for enhanced avalanche multiplication of current through the device when the FET is on, and to remove the body charge when the FET is off. The FET has an electrically floating body and is substantially electrically isolated from the substrate. The present invention provides a high resistance path coupling the floating body of the FET to the source of the FET, such that the resistor enables the device to act as a floating body for active switching purposes and as a grounded body in a standby mode to reduce leakage current. The high resistance path has a resistance of at least 1 M-ohm, and comprises a polysilicon resistor which is fabricated by using a split polysilicon process in which a buried contact mask opens a hole in a first polysilicon layer to allow a second polysilicon layer to contact the substrate.

Having thus described our invention, what we claim as new, and desire to secure by letters patent is: 
     
       1. In a field effect transistor fabricated in a substrate with a source, drain and gate, and wherein the field effect transistor has an electrically floating body and is substantially electrically isolated from the substrate, the improvement comprising a high resistance path coupling the floating body of the field effect transistor to the source of the field effect transistor, wherein the resistor enables the device to act as a floating body for active switching purposes and as a grounded body in a standby mode to reduce leakage current. 
     
     
       2. The field effect transistor of claim 1, wherein the high resistance path has a resistance of at least 1 M-ohm. 
     
     
       3. The field effect transistor of claim 1, wherein the transistor is fabricated in SOI CMOS. 
     
     
       4. The field effect transistor of claim 1, wherein the resistor comprises a polysilicon resistor. 
     
     
       5. The field effect transistor of claim 4, wherein the polysilicon resistor is constructed by using a split polysilicon process in which a buried contact mask opens a hole in a first polysilicon layer to allow a second polysilicon layer to contact the substrate. 
     
     
       6. The field effect transistor of claim 4, wherein the resistor polysilicon is patterned at the same time as the gate polysilicon with the same application of a PC mask. 
     
     
       7. The field effect transistor of claim 6, wherein the PC mask comprises a nitride hardmask which prevents silicidation of the polysilicon gate layer and prevents penetration of the source and drain ion implants, such that the polysilicon remains unsilicided and intrinsically doped to provide a high resistance path for the body charge to the source. 
     
     
       8. The field effect transistor of claim 1, wherein the drain provides for enhanced avalanche multiplication of current through the device. 
     
     
       9. The field effect transistor of claim 8, wherein the drain region is implanted with a relatively high dose halo implant, which results in an extremely abrupt junction to enhance the avalanche multiplication current through the device. 
     
     
       10. The field effect transistor of claim 9, wherein most of the drain is masked prior to implanting the high dose halo implant. 
     
     
       11. The field effect transistor of claim 8, wherein the implant is performed over the entire width of the drain.