Inventor

LIU KAIPING

US31 patents

⚠️ This page may combine multiple inventors who share the name “LIU KAIPING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIU KAIPING

TEXAS INSTRUMENTS INC

Method to produce localized halo for MOS transistor

Method to produce localized halo for MOS transistor

Method to fabricate optimal HDD with dual diffusion process to optimize transistor drive current junction capacitance, tunneling current and channel dopant loss

Semiconductor device having a localized halo implant therein and method of manufacture therefor

Transistors, integrated circuits, systems, and processes of manufacture with improved work function modulation

System for reducing segregation and diffusion of halo implants into highly doped regions

Process method of source drain spacer engineering to improve transistor capacitance

Plasma treatment for thin film resistors on integrated circuits

Multiple depth vias in an integrated circuit

Semiconductor device having an angled compensation implant and method of manufacture therefor

Transistor with bottomwall/sidewall junction capacitance reduction region and method

Silicide method for CMOS integrated circuits

System and method for extraction of C-V characteristics of ultra-thin oxides

Semiconductor device having an implanted precipitate region and a method of manufacture therefor

Method of manufacturing a semiconductor device having a localized halo implant

System and method for addressing junction capacitances in semiconductor devices

Low cost demos transistor with improved CHC immunity

Low leakage capacitor for analog floating-gate integrated circuits

Semiconductor device having a dislocation loop located within a boundary created by source/drain regions and a method of manufacture therefor

High precision capacitor dielectric

Multiple depth vias in an integrated circuit

Method of manufacturing transistor having germanium implant region on the sidewalls of the polysilicon gate electrode

Analog floating-gate capacitor with improved data retention in a silicided integrated circuit

Using oxynitride spacer to reduce parasitic capacitance in CMOS devices

Reducing the migration of grain boundaries

Reducing the migration of grain boundaries

Low cost demos transistor with improved CHC immunity

High precision capacitor dielectric

Multiple depth vias in an integrated circuit

LIU KAIPING

Analog floating-gate capacitor with improved data retention in a silicided integrated circuit

KHAN IMRAN MAHMOOD

Low leakage capacitor for analog floating-gate integrated circuits