Multiple depth vias in an integrated circuit

Abstract

An integrated circuit with vias with different depths stopping on etch stop layers with different thicknesses. A method of simultaneously etching vias with different depths without causing etch damage to the material being contacted by the vias.

What is claimed is: 
     
       1. An integrated circuit, comprising:
 a first level of interconnect; 
 an first etch stop layer with a first thickness on said first level of interconnect; 
 a first ILD layer on said first etch stop layer; 
 a device formed on said first ILD layer; 
 a second etch stop layer with a second thickness approximately equal to said first thickness plus an additional thickness approximately equal to the depth of a deep via minus the depth of a shallow via times the ratio of an etch rate of said etch stop layer to an etch rate of said ILD in a plasma ILD via etch; 
 a second ILD layer formed over said device; 
 a second level of interconnect formed on said second ILD layer; 
 a deep via through said first etch stop layer and through said first ILD layer and through said second ILD layer connecting said second level of interconnect to said first level of interconnect; and 
 a shallow via through said second etch stop layer and through said second ILD layer connecting said second level of interconnect to said device. 
 
     
     
       2. The integrated circuit of  claim 1  further comprising:
 an third depth via; 
 where said device is a MIM capacitor; 
 where said second etch stop layer is on a bottom plate of said MIM capacitor; 
 a third etch stop layer on a top plate of said MIM capacitor with a third thickness approximately equal to said first thickness minus said second thickness plus a thickness approximately equal to the depth of said deep via minus the depth of said third depth via times the ratio of the etch rate of the etch stop layer to the etch rate of the ILD in said plasma ILD via etch; and 
 where said third etch stop layer is on top of a top plate of said MIM capacitor and said third depth via connects said second level of interconnect to said top capacitor plate. 
 
     
     
       3. The integrated circuit of  claim 1  where said device is a resistor, where a first shallow via connects said second level of interconnect to a first head of said resistor and where a second shallow via connects said second level of interconnect to a second head of said resistor.