Inventor

SHIH SHENG-HUNG

TW65 patents

⚠️ This page may combine multiple inventors who share the name “SHIH SHENG-HUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHIH SHENG-HUNG

TAIWAN SEMICONDUCTOR MFG CO LTD

Top electrode blocking layer for RRAM device

Perpendicular magnetic tunneling junction (MTJ) for improved magnetoresistive random-access memory (MRAM) process

RRAM cell with PMOS access transistor

RRAM device with data storage layer having increased height

RRAM cell structure with laterally offset BEVA/TEVA

Semiconductor device including memory and logic circuit having FETs with ferroelectric layer and manufacturing methods thereof

Top electrode for device structures in interconnect

RRAM cell structure with laterally offset BEVA/TEVA

Memory cells breakdown protection

Method for forming a flat bottom electrode via (BEVA) top surface for memory

Memory device and fabrication thereof

Semiconductor device and method for manufacturing the same

FeRAM decoupling capacitor

FeRAM MFM structure with selective electrode etch

Memory cell having top and bottom electrodes defining recesses

Semiconductor device and manufacturing method thereof

Top electrode for device structures in interconnect

RRAM cell structure with laterally offset BEVA/TEVA

Step height reduction of memory element

RRAM device with data storage layer having increased height

RRAM cell with PMOS access transistor

Flat bottom electrode via (BEVA) top surface for memory

Method of forming memory device

Method and apparatus for reading RRAM cell

Method and apparatus for reading RRAM cell

Method and apparatus for reading RRAM cell

RRAM cell structure with laterally offset BEVA/TEVA

Method and structures pertaining to improved ferroelectric random-access memory (FeRAM)

Top electrode for device structures in interconnect

Semiconductor device

Interfacial layer with high texture uniformity for ferroelectric layer enhancement

Ferroelectric memory device with blocking layer

Integrated circuit and method for manufacturing the same

MFM device with an enhanced bottom electrode

Semiconductor device and method of forming the same

FeRAM MFM structure with selective electrode etch

FeRAM decoupling capacitor

Semiconductor device and method for manufacturing the same

Semiconductor device and method of fabricating the same

Semiconductor device and method of forming the same

Flat bottom electrode via (BEVA) top surface for memory

Memory cell having a top electrode interconnect arranged laterally from a recess

FeRAM MFM structure with selective electrode etch

Integrated circuit and method for manufacturing the same

Method and structures pertaining to improved ferroelectric random-access memory (FeRAM)

Integrated circuit structure and method of forming the same

Semiconductor device and method of forming the same

Method for forming a flat bottom electrode via (BEVA) top surface for memory

TAIWAN SEMICONDUCTOR MFG

Resistance variable memory structure and method of forming the same

Resistive random access memory and manufacturing method thereof