FeRAM MFM structure with selective electrode etch

Abstract

In some embodiments, the present disclosure relates to a method of forming an integrated chip including forming a ferroelectric layer over a bottom electrode layer, forming a top electrode layer over the ferroelectric layer, performing a first removal process to remove peripheral portions of the bottom electrode layer, the ferroelectric layer, and the top electrode layer, and performing a second removal process using a second etch that is selective to the bottom electrode layer and the top electrode layer to remove portions of the bottom electrode layer and the top electrode layer, so that after the second removal process the ferroelectric layer has a surface that protrudes past a surface of the bottom electrode layer and the top electrode layer.

What is claimed is: 
     
       1. An integrated chip, comprising:
 one or more lower interconnect layers arranged within one or more stacked inter-layer dielectric (ILD) layers over a substrate; 
 a first bottom electrode layer disposed over the one or more lower interconnect layers; 
 a second bottom electrode layer disposed over the first bottom electrode layer; 
 a first top electrode layer disposed over the second bottom electrode layer; and 
 a ferroelectric layer disposed between the second bottom electrode layer and the first top electrode layer, 
 wherein the ferroelectric layer is wider than the second bottom electrode layer and is wider than the first top electrode layer, and wherein the first bottom electrode layer is wider than the ferroelectric layer, and 
 wherein the ferroelectric layer has outer sidewalls with a first surface roughness, and the first bottom electrode layer has outer sidewalls with a second surface roughness, and the first surface roughness is greater than the second surface roughness. 
 
     
     
       2. The integrated chip of  claim 1 , wherein the ferroelectric layer contacts a first surface of the second bottom electrode layer and a second surface of the first top electrode layer. 
     
     
       3. The integrated chip of  claim 1 , wherein widths of the ferroelectric layer, the second bottom electrode layer, and the first bottom electrode layer are measured in a first direction parallel to a bottommost surface of the first bottom electrode layer. 
     
     
       4. The integrated chip of  claim 1 , wherein the ferroelectric layer comprises a protrusion extending past outer surfaces of the first top electrode layer and the second bottom electrode layer, wherein the protrusion is confined between lines extending along a first surface of the second bottom electrode layer and a second surface of the first top electrode layer. 
     
     
       5. The integrated chip of  claim 4 , wherein the protrusion has a thickness measured in a second direction normal to the first surface that is less than a distance between the first surface of the second bottom electrode layer and the second surface of the first top electrode layer measured in the second direction. 
     
     
       6. The integrated chip of  claim 1 , further comprising a second top electrode layer overlying the first top electrode layer, wherein the second top electrode layer is wider than the ferroelectric layer. 
     
     
       7. The integrated chip of  claim 1 , wherein the ferroelectric layer has upper and lower surfaces with a third surface roughness, and the first surface roughness is greater than the third surface roughness. 
     
     
       8. An integrated chip, comprising:
 one or more lower interconnect layers arranged within one or more stacked inter-layer dielectric (ILD) layers over a substrate; 
 a bottom electrode disposed over the one or more lower interconnect layers; 
 a top electrode disposed over the bottom electrode; 
 a ferroelectric layer disposed between and contacting a first surface of the bottom electrode and a second surface of the top electrode, wherein the ferroelectric layer comprises a protrusion; and 
 a first ILD surrounding the protrusion and comprising a first portion both directly beneath the protrusion and above the first surface and a second portion both directly above the protrusion and beneath the second surface, 
 wherein the protrusion has a thickness measured in a first direction normal to the first surface, where the thickness is less than a distance between the first surface of the bottom electrode and the second surface of the top electrode measured in the first direction, 
 wherein the protrusion has a topmost surface that is between the first surface of the bottom electrode and the second surface of the top electrode. 
 
     
     
       9. The integrated chip of  claim 8 , wherein the protrusion extends past outer surfaces of the top electrode and the bottom electrode along a second direction that is perpendicular to the first direction, the protrusion confined between lines extending along the first surface and the second surface. 
     
     
       10. The integrated chip of  claim 8 , wherein the protrusion has a third surface that connects a fourth surface and a fifth surface of the protrusion, wherein the first surface has a greater surface roughness than the second and third surfaces of the protrusion. 
     
     
       11. The integrated chip of  claim 10 , wherein the bottom electrode has a first outer surface substantially parallel to the third surface of the protrusion, and wherein the third surface of the protrusion has a greater surface roughness than the first outer surface of the bottom electrode. 
     
     
       12. The integrated chip of  claim 8 , further comprising:
 an additional layer of the top electrode disposed over the top electrode; and 
 second ILD layer extending directly between the additional layer and the ferroelectric layer. 
 
     
     
       13. The integrated chip of  claim 12 , wherein the additional layer of the top electrode has a width about equal to a width of the ferroelectric layer. 
     
     
       14. The integrated chip of  claim 8 , wherein the protrusion further comprises an outer surface extending in the first direction and contacting the topmost surface of the protrusion, wherein the outer surface has a height less than a distance between the first surface of the bottom electrode and the topmost surface of the protrusion measured in the first direction. 
     
     
       15. The integrated chip of  claim 8 , wherein the bottom electrode has a first width and the top electrode has a second width substantially equal to the first width. 
     
     
       16. An integrated chip, comprising:
 one or more lower interconnect layers arranged within one or more stacked inter-layer dielectric (ILD) layers over a substrate; 
 
       a bottom electrode disposed over the one or more lower interconnect layers;
 a top electrode disposed over the bottom electrode; and 
 a ferroelectric layer disposed between the bottom electrode and the top electrode and having a first lower surface a first height above a bottom surface of the bottom electrode, a second lower surface a second height above the bottom surface of the bottom electrode, and a first upper surface a third height above the bottom surface of the bottom electrode and below a top surface of the ferroelectric layer, wherein the second height is greater than the first height, and the third height is greater than the second height, and wherein the ferroelectric layer comprises a protrusion extending past outer sidewalls of the bottom electrode and the top electrode, and wherein the first upper surface and the second lower surface surround the protrusion. 
 
     
     
       17. The integrated chip of  claim 16 , wherein the first upper surface is directly above the second lower surface. 
     
     
       18. The integrated chip of  claim 16 , wherein the protrusion continuously surrounds a center portion of the ferroelectric layer, wherein the first lower surface and the top surface are outer surfaces of the center portion. 
     
     
       19. The integrated chip of  claim 16 , wherein the first lower surface directly contacts the bottom electrode and the top surface of the ferroelectric layer directly contacts the top electrode. 
     
     
       20. The integrated chip of  claim 16 , further comprising:
 a first outer surface of the ferroelectric layer connecting the first upper surface and the second lower surface, the first outer surface having a first surface roughness; and 
 a second outer surface of the top electrode, the second outer surface having a second surface roughness that is less than the first surface roughness.