Inventor
GABRIEL CALVIN TODD
US21 patents
⚠️ This page may combine multiple inventors who share the name “GABRIEL CALVIN TODD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
VLSI TECHNOLOGY INC
10 patentsUS6297170B1Oct 2, 2001
Sacrificial multilayer anti-reflective coating for mos gate formation
VLSI TECHNOLOGY INC240 citations97
US6107158AAug 22, 2000
Method of manufacturing a trench structure in a semiconductor substrate
VLSI TECHNOLOGY INC82 citations95
US5776821AJul 7, 1998
Method for forming a reduced width gate electrode
VLSI TECHNOLOGY INC80 citations95
US5939765AAug 17, 1999
Sidewall profile
VLSI TECHNOLOGY INC19 citations91
US5882982AMar 16, 1999
Trench isolation method
VLSI TECHNOLOGY INC30 citations91
US6207565B1Mar 27, 2001
Integrated process for ashing resist and treating silicon after masked spacer etch
VLSI TECHNOLOGY INC22 citations90
US6027950AFeb 22, 2000
Method for achieving accurate SOG etchback selectivity
VLSI TECHNOLOGY INC8 citations73
US6013558AJan 11, 2000
Silicon-enriched shallow trench oxide for reduced recess during LDD spacer etch
VLSI TECHNOLOGY INC15 citations73
US5821163AOct 13, 1998
Method for achieving accurate SOG etchback selectivity
VLSI TECHNOLOGY INC7 citations73
US5976987ANov 2, 1999
In-situ corner rounding during oxide etch for improved plug fill
VLSI TECHNOLOGY INC3 citations62
KONINKL PHILIPS ELECTRONICS NV
5 patentsUS6545338B1Apr 8, 2003
Methods for implementing co-axial interconnect lines in a CMOS process for high speed RF and microwave applications
KONINKL PHILIPS ELECTRONICS NV63 citations95
US6541359B1Apr 1, 2003
Optimized gate implants for reducing dopant effects during gate etching
KONINKL PHILIPS ELECTRONICS NV6 citations69
US6627536B1Sep 30, 2003
Semiconductor blocking layer for preventing UV radiation damage to MOS gate oxides
KONINKL PHILIPS ELECTRONICS NV4 citations63
US6794294B1Sep 21, 2004
Etch process that resists notching at electrode bottom
KONINKL PHILIPS ELECTRONICS NV4 citations62
US6822291B2Nov 23, 2004
Optimized gate implants for reducing dopant effects during gate etching
KONINKL PHILIPS ELECTRONICS NV0 citations47
PHILIPS ELECTRONICS NA
3 patentsUS6569757B1May 27, 2003
Methods for forming co-axial interconnect lines in a CMOS process for high speed applications
PHILIPS ELECTRONICS NA74 citations95
US6361706B1Mar 26, 2002
Method for reducing the amount of perfluorocompound gas contained in exhaust emissions from plasma processing
PHILIPS ELECTRONICS NA31 citations92
US6342428B1Jan 29, 2002
Method for a consistent shallow trench etch profile
PHILIPS ELECTRONICS NA28 citations90