Inventor
SUKEGAWA NAONOBU
JP21 patents
⚠️ This page may combine multiple inventors who share the name “SUKEGAWA NAONOBU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
HITACHI LTD
18 patentsUS7293092B2Nov 6, 2007
Computing system and control method
HITACHI LTD101 citations98
US5978830ANov 2, 1999
Multiple parallel-job scheduling method and apparatus
HITACHI LTD167 citations97
US5898883AApr 27, 1999
Memory access mechanism for a parallel processing computer system with distributed shared memory
HITACHI LTD59 citations96
US5606686AFeb 25, 1997
Access control method for a shared main memory in a multiprocessor based upon a directory held at a storage location of data in the memory after reading data to a processor
HITACHI LTD90 citations96
US5968135AOct 19, 1999
Processing instructions up to load instruction after executing sync flag monitor instruction during plural processor shared memory store/load access synchronization
HITACHI LTD105 citations94
US5778429AJul 7, 1998
Parallel processor system including a cache memory subsystem that has independently addressable local and remote data areas
HITACHI LTD64 citations94
US6466988B1Oct 15, 2002
Multiprocessor synchronization and coherency control system
HITACHI LTD61 citations93
US7191294B2Mar 13, 2007
Method for synchronizing processors in a multiprocessor system
HITACHI LTD24 citations92
US6263406B1Jul 17, 2001
Parallel processor synchronization and coherency control method and system
HITACHI LTD60 citations91
US5978894ANov 2, 1999
Method of interprocessor data transfer using a network, virtual addresses and paging, a buffer, flags, data transfer status information and user accessible storage areas in main memory
HITACHI LTD21 citations91
US7958508B2Jun 7, 2011
Method of power-aware job management and computer system
HITACHI LTD11 citations84
US7366814B2Apr 29, 2008
Heterogeneous multiprocessor system and OS configuration method thereof
HITACHI LTD13 citations84
US7739530B2Jun 15, 2010
Method and program for generating execution code for performing parallel processing
HITACHI LTD10 citations83
US6295579B1Sep 25, 2001
Parallel processor system including a cache memory subsystem that has independently addressable local and remote data areas
HITACHI LTD11 citations72
US7159079B2Jan 2, 2007
Multiprocessor system
HITACHI LTD3 citations63
US7155540B2Dec 26, 2006
Data communication method in shared memory multiprocessor system
HITACHI LTD3 citations63
US7895399B2Feb 22, 2011
Computer system and control method for controlling processor execution of a prefetech command
HITACHI LTD4 citations62
US6335903B2Jan 1, 2002
Memory system
HITACHI LTD0 citations35