Inventor
SYWYK STEFAN P
US21 patents
⚠️ This page may combine multiple inventors who share the name “SYWYK STEFAN P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
CYPRESS SEMICONDUCTOR CORP
15 patentsUS6751755B1Jun 15, 2004
Content addressable memory having redundancy capabilities
CYPRESS SEMICONDUCTOR CORP64 citations96
US6005796ADec 21, 1999
Single ended simpler dual port memory cell
CYPRESS SEMICONDUCTOR CORP50 citations96
US5768196AJun 16, 1998
Shift-register based row select circuit with redundancy for a FIFO memory
CYPRESS SEMICONDUCTOR CORP74 citations95
US6731566B1May 4, 2004
Single ended simplex dual port memory cell
CYPRESS SEMICONDUCTOR CORP28 citations92
US6697275B1Feb 24, 2004
Method and apparatus for content addressable memory test mode
CYPRESS SEMICONDUCTOR CORP40 citations92
US6661716B1Dec 9, 2003
Write method and circuit for content addressable memory
CYPRESS SEMICONDUCTOR CORP19 citations92
US6647457B1Nov 11, 2003
Content addressable memory having prioritization of unoccupied entries
CYPRESS SEMICONDUCTOR CORP45 citations92
US6515884B1Feb 4, 2003
Content addressable memory having reduced current consumption
CYPRESS SEMICONDUCTOR CORP43 citations92
US6262912B1Jul 17, 2001
Single ended simplex dual port memory cell
CYPRESS SEMICONDUCTOR CORP26 citations92
US5765214AJun 9, 1998
Memory access method and apparatus and multi-plane memory device with prefetch
CYPRESS SEMICONDUCTOR CORP36 citations92
US6181595B1Jan 30, 2001
Single ended dual port memory cell
CYPRESS SEMICONDUCTOR CORP13 citations74
US5336938AAug 9, 1994
Apparatus for generating an asynchronous status flag with defined minimum pulse
CYPRESS SEMICONDUCTOR CORP14 citations74
US6933757B1Aug 23, 2005
Timing method and apparatus for integrated circuit device
CYPRESS SEMICONDUCTOR CORP5 citations63
US6002283ADec 14, 1999
Apparatus for generating an asynchronous status flag with defined minimum pulse
CYPRESS SEMICONDUCTOR CORP4 citations63
US5715205AFeb 3, 1998
Memory with a selectable data width and reduced decoding logic
CYPRESS SEMICONDUCTOR CORP4 citations63
NVIDIA CORP
3 patentsUS12395175B2Aug 19, 2025
Level-shifter having a wide operating range, a fast output fall delay and improved rise time
NVIDIA CORP0 citations61
US12131775B2Oct 29, 2024
Keeper-free volatile memory system
NVIDIA CORP0 citations58
US11804262B2Oct 31, 2023
Area efficient memory cell read disturb mitigation
NVIDIA CORP0 citations58