Inventor

TRAN THANG M

US135 patents

⚠️ This page may combine multiple inventors who share the name “TRAN THANG M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TRAN THANG M

ADVANCED MICRO DEVICES INC

Superscalar microprocessor configured to predict return addresses from a return stack storage

Superscalar microprocessor employing a way prediction unit to predict the way of an instruction fetch address and to concurrently provide a branch prediction address corresponding to the fetch address

Data address prediction structure and a method for operating the same

Superscalar microprocessor configured to predict return addresses from a return stack storage

Instruction fetch unit configured to provide sequential way prediction for sequential instruction fetches

Speculative store buffer

Way prediction logic for cache array

System for using a data history table to select among multiple data prefetch algorithms

Load/store unit with multiple oldest outstanding instruction pointers for completing store and load/store miss instructions

Way prediction unit and a method for operating the same

Apparatus and method for aligning variable byte-length instructions to a plurality of issue positions

Apparatus and method for resolving dependencies among a plurality of instructions within a storage device

Apparatus for controlling execution of a program in a computing device

Apparatus having hierarchically arranged decoders concurrently decoding instructions and shifting instructions not ready for execution to vacant decoders higher in the hierarchy

Three state branch history using one bit in a branch prediction mechanism

Superscalar microprocessor load/store unit employing a unified buffer and separate pointers for load and store operations

Reverse TLB for providing branch target address in a microprocessor having a physically-tagged cache

Prefetch buffer which stores a pointer indicating an initial predecode position

Way prediction logic for cache array

Pipelined instruction cache and branch prediction mechanism therefor

Fetching instructions from an instruction cache using sequential way prediction

Superscalar microprocessor configured to predict return addresses from a return stack storage

Number of pipeline stages and loop length related counter differential based end-loop prediction

Branch selectors associated with byte ranges within an instruction cache for rapidly identifying branch predictions

Speculative register file for storing speculative register states and removing dependencies between instructions utilizing the register

Branch prediction storage for storing branch prediction information such that a corresponding tag may be routed with the branch instruction

Shared branch prediction structure

Reorder buffer employing last in buffer and last in line bits

Data memory unit and method for storing data into a lockable cache in one clock cycle by previewing the tag array

Instruction cache configured to provide instructions to a microprocessor having a clock cycle time less than a cache access time of said instruction cache

Byte queue divided into multiple subqueues for optimizing instruction selection logic

Dependency table for reducing dependency checking hardware

Dependency table for reducing dependency checking hardware

Invalid instruction scan unit for detecting invalid predecode data corresponding to instructions being fetched

Predecode buffer including buffer pointer indicating another buffer for predecoding

Reorder buffer configured to allocate storage for instruction results corresponding to predefined maximum number of concurrently receivable instructions independent of a number of instructions received

Instruction cache configured to provide instructions to a microprocessor having a clock cycle time less than a cache access time of said instruction cache

Reverse TLB for providing branch target address in a microprocessor having a physically-tagged cache

Microprocessor including virtual address branch prediction and current page register to provide page portion of virtual and physical fetch address

Recorder buffer and a method for allocating a fixed amount of storage for instruction results independent of a number of concurrently dispatched instructions

Superscalar microprocessor including a decoded instruction cache configured to receive partially decoded instructions

Branch prediction mechanism employing branch selectors to select a branch prediction

Superscalar microprocessor employing a future file for storing results into multiportion registers

Reorder buffer having a future file for storing speculative instruction execution results

Apparatus for efficiently providing memory operands for instructions

Reorder buffer having an improved future file for storing speculative instruction execution results

Speculative register storage for storing speculative results corresponding to register updated by a plurality of concurrently recorded instruction

Multi-chip superscalar microprocessor module

Storage device having varying access times and a superscalar microprocessor employing the same

TRAN THANG M

Data processing system operable in single and multi-thread modes and having multiple caches and method of operation