Invalid instruction scan unit for detecting invalid predecode data corresponding to instructions being fetched

Abstract

An instruction scanning unit for a superscalar microprocessor is disclosed. The instruction scanning unit processes start, end, and functional byte information (or predecode data) associated with a plurality of contiguous instruction bytes. The processing of start byte information and end byte information is performed independently and in parallel, and the instruction scanning unit produces a plurality of scan values which identify valid instructions within the plurality of contiguous instruction bytes. Additionally, the instruction scanning unit is scaleable. Multiple instruction scanning units may be operated in parallel to process a larger plurality of contiguous instruction bytes. Furthermore, the instruction scanning unit detects error conditions in the predecode data in parallel with scanning to locate instructions. Moreover, in parallel with the error checking and scanning to locate instructions, MROM instructions are located for dispatch to an MROM unit.

What is claimed is: 
     
       1. An instruction scanning unit comprising: at least one scan block configured to scan predecode information corresponding to a set of instruction bytes in order to locate instructions for dispatch to an instruction alignment unit; and   an invalid instruction scan unit configured to scan said predecode information in parallel with said at least one scan block, said invalid instruction scan unit configured to detect invalid predecode information and to identify, via an invalid instruction pointer, a byte within said set of instruction bytes at which predecoding is to be performed to generate valid predecode information.   
     
     
       2. The instruction scanning unit as recited in claim 1 wherein said invalid instruction scan unit is further configured to identify a type of invalidity detected within said predecode information. 
     
     
       3. The instruction scanning unit as recited in claim 2 wherein said predecode information comprises a plurality of start bits, a plurality of end bits, and a plurality of functional bits, and wherein each of said plurality of start bits corresponds to a different one of said set of instruction bytes, and wherein each of said plurality of end bits corresponds to said different one of said set of instruction bytes, and wherein each of said plurality of functional bits corresponds to said different one of said set of instruction bytes. 
     
     
       4. The instruction scanning unit as recited in claim 3 wherein said type of invalidity comprises one of said plurality of start bits corresponding to a start pointer identifying a first instruction byte being fetched within said set of instruction bytes being clear. 
     
     
       5. The instruction scanning unit as recited in claim 4 wherein said invalid instruction pointer comprises said start pointer. 
     
     
       6. The instruction scanning unit as recited in claim 3 wherein said type of invalidity comprises one of said plurality of start bits corresponding to a second one of said set of instruction bytes immediately subsequent to a first one of said set of instruction bytes corresponding to a set one of said end bits being clear. 
     
     
       7. The instruction scanning unit as recited in claim 6 wherein said invalid instruction pointer indicates said second one of said set of instruction bytes. 
     
     
       8. The instruction scanning unit as recited in claim 3 wherein said type of invalidity comprises one of said plurality of start bits being set, and a plurality of said plurality of end bits subsequent to said one of said plurality of start bits being clear, wherein said plurality of said plurality of end bits is greater, in number, than a maximum number of bytes allowable in an instruction. 
     
     
       9. The instruction scanning unit as recited in claim 8 wherein said invalid instruction pointer comprises an indication of one of said set of instruction bytes corresponding to said one of said plurality of start bits. 
     
     
       10. The instruction scanning unit as recited in claim 3 wherein said type of invalidity comprises one of said plurality of start bits being set and a second one of said start bits being set prior to encountering one of said plurality of end bits being set. 
     
     
       11. The instruction scanning unit as recited in claim 10 wherein said invalid instruction pointer indicates one of said set of instruction bytes corresponding to said one of said plurality of start bits. 
     
     
       12. A method for detecting invalid predecode data, comprising: scanning said predecode data for validity in parallel with locating instructions via said predecode data; and   determining an invalid instruction pointer which indicates a byte at which said predecode data becomes invalid.   
     
     
       13. The method as recited in claim 12 further comprising transmitting said invalid instruction pointer to a prefetch/predecode unit. 
     
     
       14. The method as recited in claim 13 wherein said prefetch/predecode unit is configured to initiate predecoding at a byte indicated by said invalid instruction pointer. 
     
     
       15. The method as recited in claim 12 wherein said predecode data comprises a plurality of start bits, a plurality of end bits, and a plurality of functional bits.