Inventor

FULFORD H JIM

US196 patents

⚠️ This page may combine multiple inventors who share the name “FULFORD H JIM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FULFORD H JIM

ADVANCED MICRO DEVICES INC

Semiconductor device having metal gate electrode and titanium or tantalum nitride gate dielectric barrier layer and process of fabrication thereof

Method of making gate dielectric for sub-half micron MOS transistors including a graded dielectric constant

Method of forming high pressure silicon oxynitride gate dielectrics

Transistor and a method for forming the transistor with elevated and/or relatively shallow source/drain regions to achieve enhanced gate electrode formation

Method for filling trenches

Method of forming ultra thin gate dielectric for high performance semiconductor devices

Method of fabricating a transistor with a dielectric underlayer and device incorporating same

Advanced CMOS circuitry that utilizes both sides of a wafer surface for increased circuit density

Semiconductor device with asymmetric PMOS source/drain implant and method of manufacture thereof

Process for formation of isolation trenches with high-K gate dielectrics

Semiconductor fabrication employing implantation of excess atoms at the edges of a trench isolation structure

Method of making a semiconductor device with self-aligned active, lightly-doped drain, and halo regions

Semiconductor device with vertical halo region and methods of manufacture

Reduction of dopant diffusion by the co-implantation of impurities into the transistor gate conductor

Integrated circuit incorporating a memory cell and a transistor elevated above an insulating base

Salicide and gate dielectric formed from a single layer of refractory metal

High K integration of gate dielectric with integrated spacer formation for high speed CMOS

Transistor formation with local interconnect overetch immunity

Semiconductor structure having multiple thicknesses of high-K gate dielectrics and process of manufacture therefor

Disposable sidewall oxidation fabrication method for making a transistor having an ultra short channel length

Adjusting the size of conductive lines based upon contact size

Method of making dual channel gate oxide thickness for MOSFET transistor design

Transistor formation with LI overetch immunity

Short channel length MOSFET transistor

High performance MOSFET with low resistance design

Reduction of dopant diffusion by the co-implantation of impurities into the transistor gate conductor

High dielectric constant gate dielectric integrated with nitrogenated gate electrode

Method and apparatus for providing etch uniformity using zoned temperature control

Apparatus for filling trenches

Semiconductor device having a tri-layer gate insulating dielectric

Semiconductor device fabrication using a sacrificial plug for defining a region for a gate electrode

Semiconductor device having a PMOS device with a source/drain region formed using a heavy atom p-type implant and method of manufacture thereof

Resistance to gate dielectric breakdown at the edges of shallow trench isolation structures

Method of forming semiconductor devices using gate electrode length and spacer width for controlling drivecurrent strength

High performance MOSFET with modulated channel gate thickness

High K gate electrode

Method of making an elevated source/drain with enhanced graded sidewalls for transistor scaling integrated with spacer formation

Semiconductor device having self-aligned asymmetric source/drain regions and method of fabrication thereof

Method of forming semiconductor devices using gate electrode length and spacer width for controlling drive current strength

Method of forming semiconductor devices using gate electrode dimensions and dopant concentration for controlling drive current strength

Isolation structure having implanted silicon atoms at the top corner of the isolation trench filling vacancies and interstitial sites

Method of forming electrode for high performance semiconductor devices

Self-aligning silicon oxynitride stack for improved isolation structure

Method for forming a retrograde impurity profile

Trench and gate dielectric formation for semiconductor devices

TOKYO ELECTRON LTD

Architecture design and process for 3D logic and 3D memory

High performance nanosheet fabrication method with enhanced high mobility channel elements

Method of making multiple nano layer transistors to enhance a multiple stack CFET performance

3D complementary metal oxide semiconductor (CMOS) device and method of forming the same

AMD INC ADVANCED MICRO DEVICES

Method of making disposable channel masking for both source/drain and LDD implant and subsequent gate fabrication