Inventor

ANSARI AHMAD R

US62 patents

⚠️ This page may combine multiple inventors who share the name “ANSARI AHMAD R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ANSARI AHMAD R

XILINX INC

Custom code processing in PGA by providing instructions from fixed logic processor portion to programmable dedicated processor portion

User configurable on-chip memory system

Testing of an integrated circuit having an embedded processor

Processor local bus bridge for an embedded processor block core in an integrated circuit

Error correction for interconnect circuits

Method and apparatus for synchronization of shared memory in a multiprocessor system

Memory controller interface for an embedded processor block core in an integrated circuit

Device control register for a processor block

Method and apparatus for synchronized buses

Floor planning for programmable gate array having embedded fixed logic circuitry

Translation of commands in an interconnection of an embedded processor block core in an integrated circuit

Method of and circuit for enabling variable latency data transfers

Method and system for handling an instruction not supported in a coprocessor formed using configurable logic

Coprocessor interface controller

Processor-controller interface for non-lock step operation

Access to a bank of registers of a device control register interface using a single address

On-chip memory block circuit

Arbitration for an embedded processor block core in an integrated circuit

User-configurable error handling

Very low power real time clock

Testing of an integrated circuit having an embedded processor

Method and apparatus for processing data with a programmable gate array using fixed and programmable processors

Programmable interactive verification agent

Multi-chip structure having configurable network-on-chip

Enhancing security of internal memory

Clocking for a hardwired core embedded in a host integrated circuit device

Common input/output interface for application and debug circuitry

Deadlock-resistant bus bridge with pipeline-restricted address ranges

Shadow pipeline in an auxiliary processor unit controller

Non-destructive online testing for safety critical applications

Impactless firmware update

Configurable logic fabric including two fixed logic processors with individual interface to receive availability signal from custom operation code configured processor

Distributed configuration of programmable devices

Decoder interface

Sub-system power management control

Debug controller circuit

Protection against tamper using in-rush current

Inline configuration processor

Subsystem for configuration, security, and management of an adaptive system

NoC routing in a multi-chip device

NEC ELECTRONICS INC

Bus protocol for efficiently transferring vector data

Vector transfer system generating address error exception when vector to be transferred does not start and end on same memory page

Context switching for vector transfer unit

System for posting vector synchronization instructions to vector instruction queue to separate vector instructions from different application programs

NEC ELECTRONICS AMERICA INC

Method and apparatus for transferring vector data between memory and a register file

Vector transfer system for packing dis-contiguous vector elements together into a single bus transfer

ANSARI AHMAD R

Processor block ASIC core for embedding in an integrated circuit

Crossbar switch device for a processor block core

IBM

Speed verification of an embedded processor in a programmable logic device

XILINIX INC

Decode mode for an auxiliary processor unit controller in which an opcode is partially masked such that a configuration register defines a plurality of user defined instructions