User-configurable error handling

Abstract

A method for operating a programmable IC is disclosed. A set of circuits specified by a set of configuration data is operated in a set of programmable resources. In response to one of a set of status signals indicating an error, a value indicative of an error is stored in a respective one of a plurality of error status registers. The values stored in the plurality of error status registers are provided to an error handling circuit included in the set of circuits specified by the set of configuration data and operated in the programmable resources. At least one error handling process is performed by the error handling circuit as a function of values stored in the plurality of error status registers.

What is claimed is: 
     
       1. A method of operating a programmable IC, comprising:
 operating a set of circuits, specified by a set of configuration data, in a set of programmable resources of the programmable IC; 
 generating by a set of hardwired detection circuits coupled to the programmable resources, a set of status signals, each status signal indicating a status of a respective operating parameter of the programmable IC; 
 in response to one of the status signals indicating an error, storing a value indicative of an error in a respective one of a plurality of error status registers corresponding to the one of the status signals; 
 providing values stored in the plurality of error status registers to an error handling circuit included in the set of circuits specified by the set of configuration data and operated in the programmable resources; and 
 performing by the error handling circuit, at least one error handling process as a function of values stored in the plurality of error status registers. 
 
     
     
       2. The method of  claim 1 , further comprising maintaining the value indicative of the error in the plurality of error status registers until a reset signal is provided to the plurality of error status registers. 
     
     
       3. The method of  claim 1 , further comprising:
 masking the values of the error status registers with a mask included in the configuration data to produce a set of masked error signals; and 
 outputting an error signal as a function of the set of masked error signals. 
 
     
     
       4. The method of  claim 1 , further comprising:
 masking the values of the error status registers with a mask included in the configuration data to produce a set of masked error signals; and 
 performing a power-on reset of the programmable IC as a function of the set of masked error signals. 
 
     
     
       5. The method of  claim 1 , further comprising:
 masking the values of the error status registers with a mask specified in the set of configuration data to produce a set of masked error signals; and 
 performing a system reset of the programmable IC as a function of the set of masked error signals. 
 
     
     
       6. The method of  claim 1 , wherein each status signal in the set of status signals indicates the status of a respective one of a plurality of sub-systems in the programmable IC; and
 further comprising:
 providing the values of the error status registers as interrupts to a power management unit; and 
 resetting only a first one of the plurality of sub-systems in response to a first combination of the interrupts. 
 
 
     
     
       7. The method of  claim 6 , further comprising:
 prior to resetting the first one of the plurality of sub-systems: 
 prohibiting new data transactions from being sent to the first one of the plurality of sub-systems; and 
 completing pending data transactions of the first one of the plurality of sub-systems. 
 
     
     
       8. The method of  claim 6 , wherein:
 each status signal in the set of status signals indicates the status of a respective one of the plurality of sub-systems in the programmable IC; and 
 further comprising:
 resetting only a second one of the plurality of sub-systems in response to a second combination of the interrupts, the second combination of the interrupts being different from the first combination of the interrupts. 
 
 
     
     
       9. The method of  claim 8 , wherein:
 the first one of the plurality of sub-systems is a programmable logic sub-system, including the programmable resources; 
 the second one of the plurality of sub-systems is a processing sub-system configured to execute a program input to the programmable IC; 
 the processing sub-system is configured to, at startup of the processing sub-system, program the programmable resources of the programmable logic sub-system to implement the set of circuits; and 
 the resetting of only the first one of the plurality of sub-systems includes configuring the programmable IC to prevent the processing sub-system from programming the programmable resources. 
 
     
     
       10. A system, comprising:
 a plurality of sub-systems, including at least a programmable logic sub-system configured to implement a set of circuits specified in a set of configuration data input to the system; 
 a set of registers configured to receive and store error signals generated during operation of the system; and 
 an error handling circuit configured to receive the errors stored in the set of registers, and reset individual ones of the plurality of sub-systems as a function of the errors stored in the set of registers and a set of user defined criteria specified in the set of configuration data. 
 
     
     
       11. The system of  claim 10 , wherein:
 the plurality of sub-systems includes a processing sub-system; and 
 the error handling circuit is configured to:
 reset only the processing sub-system in response to a first combination of errors being stored by the set of registers; and 
 reset only the programmable logic sub-system in response to a second combination of errors being stored by the set of registers. 
 
 
     
     
       12. The system of  claim 11 , wherein:
 the processing sub-system is configured to, at startup of the processing sub-system, program programmable resources of the programmable logic sub-system to implement the set of circuits specified in the set of configuration data. 
 
     
     
       13. The system of  claim 11 , wherein the error handling circuit is configured to reset only the programmable logic sub-system by:
 inhibiting new data transactions from being sent to the programmable logic sub-system; 
 completing pending data transactions of the programmable logic sub-system; 
 resetting the programmable logic sub-system; and 
 in response to the programmable logic sub-system booting up, enabling new data transactions to be sent to the programmable logic sub-system. 
 
     
     
       14. The system of  claim 11 , wherein the error handling circuit is configured to reset only the processing sub-system by:
 inhibiting new data transactions from being sent to the processing sub-system; 
 completing pending data transactions of the processing sub-system; 
 inhibiting configuration of the programmable logic sub-system by the processing sub-system; 
 resetting the processing sub-system; and 
 in response to the processing sub-system booting up, enabling new data transactions to be sent to the processing sub-system and enabling configuration of the programmable logic sub-system by the processing sub-system. 
 
     
     
       15. The system of  claim 10 , wherein the set of circuits implemented by the programmable logic sub-system includes the error handling circuit. 
     
     
       16. The system of  claim 10 , further comprising an error mask circuit, configured to
 mask values of the set of registers with a mask specified in the set of configuration data to produce a set of masked error signals. 
 
     
     
       17. The system of  claim 16 , wherein the error mask circuit is further configured to perform a logical OR of the set of masked error signals to produce a user-defined error signal that indicates if any of the set of masked error signals indicates that an error has occurred. 
     
     
       18. The system of  claim 16 , wherein the error handling circuit is configured to perform the resetting of the individual ones of the plurality of sub-systems as a function of the masked error signals. 
     
     
       19. A method of operating a programmable IC, comprising:
 programming programmable resources to implement a set of circuits, specified by a set of configuration data; 
 programming firmware of a hardwired power management unit (PMU) in the programmable IC to cause the PMU to perform an action specified in the set of configuration data in response to a set of status signals indicating a combination of errors specified in the set of configuration data; 
 generating by a set of hardwired detection circuits coupled to the programmable resources, the set of status signals, each status signal indicating a status of a respective operating parameter of the programmable IC; 
 in response to one of the status signals indicating an error, storing a value indicative of an error in a respective one of a plurality of error status registers corresponding to the one of the status signals; 
 providing the values stored in the plurality of error status registers to the power management unit; and 
 performing by the PMU the action specified in the set of configuration data in response to the values stored in the plurality of error status registers indicating the combination of errors specified in the set of configuration data. 
 
     
     
       20. The method of  claim 19 , further comprising:
 providing the values stored in the plurality of error status registers to an error handling circuit included in the set of circuits specified by the set of configuration data and operated in the programmable resources; and 
 performing by the error handling circuit, at least one error handling process as a function of values stored in the plurality of error status registers.