P

Inventor

MAHAJAN RAVINDRANATH V

US51 patents
⚠️ This page may combine multiple inventors who share the name “MAHAJAN RAVINDRANATH V”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

45 patents
US9275955B2Mar 1, 2016

Integrated circuit package with embedded bridge

INTEL CORP49 citations98
US9679843B2Jun 13, 2017

Localized high density substrate routing

INTEL CORP17 citations92
US6981849B2Jan 3, 2006

Electro-osmotic pumps and micro-channels

INTEL CORP20 citations91
US11557541B2Jan 17, 2023

Interconnect architecture with silicon interposer and EMIB

INTEL CORP6 citations85
US10366951B2Jul 30, 2019

Localized high density substrate routing

INTEL CORP7 citations84
US10068852B2Sep 4, 2018

Integrated circuit package with embedded bridge

INTEL CORP8 citations84
US9716067B2Jul 25, 2017

Integrated circuit package with embedded bridge

INTEL CORP6 citations84
US9323327B2Apr 26, 2016

System and method for providing tactile feedback

INTEL CORP7 citations84
US11049798B2Jun 29, 2021

Embedded bridge with through-silicon Vias

INTEL CORP4 citations82
US10373893B2Aug 6, 2019

Embedded bridge with through-silicon vias

INTEL CORP9 citations82
US9691711B2Jun 27, 2017

Method of making an electromagnetic interference shield for semiconductor chip packages

INTEL CORP9 citations82
US12061371B2Aug 13, 2024

Patch on interposer architecture for low cost optical co-packaging

INTEL CORP2 citations73
US11894359B2Feb 6, 2024

Distributed semiconductor die and package architecture

INTEL CORP1 citations73
US11328968B2May 10, 2022

Stacked die cavity package

INTEL CORP2 citations73
US9775763B2Oct 3, 2017

Adaptive exoskeleton, control system and methods using the same

INTEL CORP4 citations73
US9685421B2Jun 20, 2017

Methods for high precision microelectronic die integration

INTEL CORP3 citations73
US11694959B2Jul 4, 2023

Multi-die ultrafine pitch patch architecture and method of making

INTEL CORP3 citations72
US6043560AMar 28, 2000

Thermal interface thickness control for a microprocessor

INTEL CORP11 citations72
US11664293B2May 30, 2023

Solid state thermoelectric cooler in silicon backend layers for fast cooling in turbo scenarios

INTEL CORP2 citations71
US11257804B2Feb 22, 2022

Distributed semiconductor die and package architecture

INTEL CORP1 citations71
US10468331B2Nov 5, 2019

Heat management system

INTEL CORP3 citations69
US11404349B2Aug 2, 2022

Multi-chip packages and sinterable paste for use with thermal interface materials

INTEL CORP2 citations68
US12218040B2Feb 4, 2025

Nested interposer with through-silicon via bridge die

INTEL CORP0 citations63
US11222847B2Jan 11, 2022

Enabling long interconnect bridges

INTEL CORP0 citations63
US9118188B2Aug 25, 2015

Wireless charging system

INTEL CORP3 citations63
US12571959B2Mar 10, 2026

Embedded photonic integrated circuits

INTEL CORP0 citations62
US12519062B2Jan 6, 2026

Multiple die package using an embedded bridge connecting dies

INTEL CORP0 citations62
US12347783B2Jul 1, 2025

Interconnect architecture with silicon interposer and EMIB

INTEL CORP0 citations62
US11901299B2Feb 13, 2024

Interconnect architecture with silicon interposer and EMIB

INTEL CORP0 citations62
US11705377B2Jul 18, 2023

Stacked die cavity package

INTEL CORP0 citations62
US11569173B2Jan 31, 2023

Bridge hub tiling architecture

INTEL CORP1 citations62
US10978423B2Apr 13, 2021

Projecting contacts and method for making the same

INTEL CORP0 citations62
US12159813B2Dec 3, 2024

Embedded bridge die with through-silicon vias

INTEL CORP0 citations61
US12142568B2Nov 12, 2024

Multi-die ultrafine pitch patch architecture of interconnect bridge over glass layer and method of making

INTEL CORP0 citations61
US11587851B2Feb 21, 2023

Embedded bridge with through-silicon vias

INTEL CORP0 citations61
US12494441B2Dec 9, 2025

BGA stiffener attachment with low Eolife adhesive strength at high solder joint stress area generated from enabling load

INTEL CORP0 citations59
US11832419B2Nov 28, 2023

Full package vapor chamber with IHS

INTEL CORP0 citations59
US11742293B2Aug 29, 2023

Multiple die package using an embedded bridge connecting dies

INTEL CORP0 citations58
US11830863B2Nov 28, 2023

Dual-sided co-packaged optics for high bandwidth networking applications

INTEL CORP0 citations56
US11217573B2Jan 4, 2022

Dual-sided co-packaged optics for high bandwidth networking applications

INTEL CORP0 citations56
US9847308B2Dec 19, 2017

Magnetic intermetallic compound interconnect

INTEL CORP0 citations52
US9076882B2Jul 7, 2015

Methods for high precision microelectronic die integration

INTEL CORP0 citations52
US11756889B2Sep 12, 2023

Ultrathin bridge and multi-die ultrafine pitch patch architecture and method of making

INTEL CORP0 citations51
US12517314B2Jan 6, 2026

High bandwidth optical interconnection architectures

INTEL CORP0 citations50
US10804117B2Oct 13, 2020

Method to enable interposer to interposer connection

INTEL CORP0 citations49

SWAMINATHAN RAJASEKARAN

2 patents

GOMES WILFRED

1 patent

MAHAJAN RAVINDRANATH V

1 patent

ALEKSOV ALEKSANDAR

1 patent

Showing the top 50 of 51 patents by PatentIndex Score.