Inventor

KATOCH ATUL

CA97 patents

⚠️ This page may combine multiple inventors who share the name “KATOCH ATUL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KATOCH ATUL

TAIWAN SEMICONDUCTOR MFG CO LTD

Systems and methods for controlling power management operations in a memory device

Fixed-level charge sharing type LCV for memory compiler

SRAM with local bit line, input/output circuit, and global bit line

Word-line driver and method of operating a word-line driver

Word-line driver and method of operating a word-line driver

Systems and methods for controlling power management operations in a memory device

Systems and methods for controlling power management operations in a memory device

Low power wake up for memory

Memory device with global and local latches

Memory circuit having data lines selectively coupled to a sense amplifier and method for operating the same

Memory circuit with assist circuit trimming

Variable voltage bit line precharge

Scan synchronous-write-through testing architectures for a memory device

Variable voltage bit line precharge

Scan synchronous-write-through testing architectures for a memory device

Memory array having disturb detector and write assistor

Word-line driver and method of operating a word-line driver

Bit line pre-charge circuit for power management modes in multi bank SRAM

Memory circuit and method of operating same

Bit line pre-charge circuit for power management modes in multi bank SRAM

Memory input hold time adjustment

Memory circuit and method of operating same

Far end driver for memory clock

Low power wake up for memory

Memory device, read clock generation circuit, and method for controlling read operation in memory device

Memory device with signal edge sharpener circuitry

Word line booster circuit and method

Robust circuit for negative bit line generation in SRAM cells

Far end driver for memory clock

Word line booster circuit and method

Memory device with signal edge sharpener circuitry

Memory architecture having first and second voltages

Memory device with global and local latches

Technique to mitigate clock generation failure at high input clock slew

Variable voltage bit line precharge

Word line delay interlock circuit for write operation

Semiconductor device including first and second clock generators

TAIWAN SEMICONDUCTOR MFG

Clamping circuit for multiple-port memory cell

Wordline driver

Power management during wakeup

Fault injection of finFET devices

Read tracking mechanism

Write assist circuit for write disturbed memory cell

Detecting write disturb in multi-port memories

KATOCH ATUL

Tracking circuit

Dual rail memory architecture

Sense amplifier with adjustable back bias

Memory circuit with switch between sense amplifier and data line and method for operating the same

Boosting supply voltage

NXP BV

Integrated circuit, electronic device and integrated circuit control method