Robust circuit for negative bit line generation in SRAM cells

Abstract

Systems and methods are provided for limiting a negative bit line voltage in a SRAM cell. A voltage limiter circuit may be implemented in a write driver to control the magnitude of negative voltage imposed on a bit line. The voltage limiter circuit can produce the required magnitude of negative bit line voltage at lower operating voltage levels. The voltage limiter circuit can also limit the magnitude of negative bit line voltage to not exceed a predetermined value. The reduction of the magnitude of the negative bit line voltage can reduce the active power of a SRAM cell.

What is claimed is: 
     
       1. A write driver configured to receive a data signal, a write signal, and a negative bit line input signal and to generate a negative bit line voltage to one of two bit lines of a memory cell, the write driver comprising:
 a capacitor responsive to a first node configured to provide a transition of the negative bit line voltage over a period of time; and 
 a voltage limiter circuit configured to control a voltage at the first node, the voltage limiter circuit being configured to limit a magnitude of the negative bit line voltage on said one of the two bit lines of the memory cell such that the magnitude does not exceed a predefined threshold. 
 
     
     
       2. The write driver of  claim 1 , wherein the voltage limiter circuit is further configured to limit the magnitude of the negative bit line voltage while permitting the negative bit line voltage to reach a write operation threshold level. 
     
     
       3. The write driver of  claim 1 , wherein the voltage limiter circuit is further configured to reduce an active power of an SRAM cell at a high operating voltage mode. 
     
     
       4. The write driver of  claim 1 , the write driver being coupled to:
 a memory array configured to receive the negative bit line voltage and to perform a write operation to the memory cell, the memory array including one or more transistors and the two bit lines; 
 a control circuit configured to generate the negative bit line input signal and the write signal; and 
 a data latch configured to generate the data signal. 
 
     
     
       5. The write driver of  claim 3 , wherein each of the two bit lines further comprise a pass gate MOSFET configured to transfer one or more write operation data signals from the write driver to the memory array. 
     
     
       6. The write driver of  claim 5 , wherein the negative bit line voltage increases a gate to source voltage of the pass gate MOSFET. 
     
     
       7. The write driver of  claim 4 , wherein the voltage limiter circuit comprises a diode circuit configured to clamp the first node at a predefined voltage level. 
     
     
       8. The write driver of  claim 7 , wherein the diode circuit comprises a transistor, and wherein:
 the source terminal of the transistor is coupled to a supply voltage node; 
 the drain terminal of the transistor is coupled to the active low negative bit line; and 
 the active low negative bit line is coupled to the first node. 
 
     
     
       9. The write driver of  claim 4 , wherein the voltage limiter circuit comprises an array of transistors configured to receive a plurality of voltage threshold selection signals and to clamp the node of an active low negative bit line at one of a plurality of predefined voltage levels that are each lower than an operating voltage of a SRAM cell based upon the plurality of voltage threshold selection signals. 
     
     
       10. The write driver of  claim 9 , wherein:
 the plurality of voltage threshold selection signals is received at the gate terminal of one or more transistors within the array of transistors; 
 the array of transistors is coupled to the active low negative bit line; and 
 the active low negative bit line is coupled to the first node. 
 
     
     
       11. A method of operating a write driver, comprising:
 receiving a data signal; 
 generating a negative bit line voltage, wherein the magnitude of the negative bit line voltage is limited to not exceed a predetermined value and permitted to reach a write operation threshold level; and 
 applying the negative bit line voltage to one of two bit lines based on the data signal. 
 
     
     
       12. The method of  claim 11 , wherein the step of limiting the magnitude of the negative bit line voltage is accomplished during a high operating voltage mode of a SRAM cell. 
     
     
       13. The method of  claim 11 , further comprising determining the magnitude of the negative bit line voltage necessary for performing a successful write operation. 
     
     
       14. The method of  claim 12 , the method reducing an active power of the SRAM cell. 
     
     
       15. A memory circuit, comprising:
 a memory array including a plurality of transistors and a plurality of bit lines that form a plurality of memory cells, the memory array being configured to receive one or more write operation data signals and to perform a write operation to a memory location; and 
 a write driver configured to receive a data signal, a write signal, and a negative bit line input signal and to generate the one or more write operation data signals including a negative bit line voltage to one of two bit lines of a particular memory cell, the write driver comprising a capacitor configured to provide a transition of the negative bit line voltage over a period of time and a voltage limiter circuit configured to limit a magnitude of the negative bit line voltage on said one of the two bit lines of the memory cell. 
 
     
     
       16. The memory circuit of  claim 15 , wherein each of the one or more bit lines further comprise a pass gate MOSFET configured to transfer the one or more write operation data signals from a write driver to the memory array. 
     
     
       17. The memory circuit of  claim 15 , the memory circuit further comprising:
 a control circuit configured to receive a clock signal and an address signal and to generate the negative bit line input signal and the write signal; and 
 a data latch configured to generate the data signal. 
 
     
     
       18. The memory circuit of  claim 15 , the voltage limiter circuit comprising a diode circuit configured to clamp a node of an active low negative bit line at a predefined voltage level such as to limit the magnitude of negative voltage that is coupled to the one of the two bit lines to not exceed a predefined threshold. 
     
     
       19. The memory circuit of  claim 15 , wherein the voltage limiter circuit comprises an array of transistors configured to clamp a node of an active low negative bit line at one of a plurality of predefined voltage levels that are each lower than an operating voltage of the SRAM cell. 
     
     
       20. The memory circuit of  claim 19 , wherein the array of transistors is configured to receive a plurality of voltage threshold selection signals and to clamp the node of the active low negative bit line at one of the plurality of predefined voltage levels based upon the plurality of voltage threshold selection signals.