Inventor · disambiguated record
Ivan Herrera Mejia
Also filed as: HERRERA MEJIA IVAN · HERRERA MEJIA IVAN RODRIGO
8 granted patents·2 pending applications·6 citations·filing 2013–2024
77Inventor score
Files withINTEL CORP10
Top patents by PatentIndex Score
10 records- 0191US12164370B2Power error monitoring and reporting within a system on chip for functional safetyINTEL CORP·Filed 2023·Granted Dec 10, 2024·2 cites·18 claims
- 0274US12038819B2Hardware software communication channel to support direct programming interface methods on FPGA-based prototype platformsINTEL CORP·Filed 2022·Granted Jul 16, 2024·1 cites·20 claims
- 0370US11669385B2Power error monitoring and reporting within a system on chip for functional safetyINTEL CORP·Filed 2019·Granted Jun 6, 2023·1 cites·25 claims
- 0465US9436244B2Adaptive control loop protection for fast and robust recovery from low-power states in high speed serial I/O applicationsINTEL CORP·Filed 2013·Granted Sep 6, 2016·2 cites·27 claims
- 0560US2024427679A1Hardware software communication channel to support direct programming interface methods on fpga-based prototype platformsINTEL CORP·Filed 2024·Application pending·0 cites
- 0654US9798369B2Indicating critical battery status in mobile devicesINTEL CORP·Filed 2016·Granted Oct 24, 2017·0 cites·20 claims
- 0752US9335808B2Indicating critical battery status in mobile devicesINTEL CORP·Filed 2013·Granted May 10, 2016·0 cites·11 claims
- 0851US11544160B2IPS SOC PLL monitoring and error reportingINTEL CORP·Filed 2019·Granted Jan 3, 2023·0 cites·25 claims
- 0947US9223365B2Method and apparatus for controlled reset sequences without parallel fuses and PLL'SINTEL CORP·Filed 2013·Granted Dec 29, 2015·0 cites·19 claims
- 1040US2023401130A1Fpga based platform for post-silicon validation of chipletsINTEL CORP·Filed 2022·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →