Inventor · disambiguated record
Sitaraman V. Iyer
Also filed as: IYER SITARAMAN · IYER SITARAMAN V
19 granted patents·4 pending applications·74 citations·filing 2006–2025
94Inventor score
Top patents by PatentIndex Score
23 records- 0196US12197357B2High performance interconnectINTEL CORP·Filed 2021·Granted Jan 14, 2025·2 cites·20 claims
- 0294US9626321B2High performance interconnectINTEL CORP·Filed 2013·Granted Apr 18, 2017·14 cites·1 claims
- 0393US10248591B2High performance interconnectINTEL CORP·Filed 2016·Granted Apr 2, 2019·5 cites·23 claims
- 0492US11741030B2High performance interconnectINTEL CORP·Filed 2020·Granted Aug 29, 2023·2 cites·20 claims
- 0592US10216674B2High performance interconnect physical layerINTEL CORP·Filed 2016·Granted Feb 26, 2019·7 cites·24 claims
- 0690US2025321910A1High performance interconnectINTEL CORP·Filed 2025·Application pending·0 cites
- 0789US9600431B2High performance interconnect physical layerINTEL CORP·Filed 2013·Granted Mar 21, 2017·8 cites·26 claims
- 0887US9612986B2High performance interconnect physical layerINTEL CORP·Filed 2014·Granted Apr 4, 2017·6 cites·20 claims
- 0985US12189550B2High performance interconnectINTEL CORP·Filed 2023·Granted Jan 7, 2025·0 cites·20 claims
- 1084US10795841B2High performance interconnect physical layerINTEL CORP·Filed 2019·Granted Oct 6, 2020·3 cites·20 claims
- 1183US7936186B1Method and apparatus for correcting duty cycle via current mode logic to CMOS converterINTEL CORP·Filed 2009·Granted May 3, 2011·13 cites·19 claims
- 1281US10002095B2High performance interconnect physical layerINTEL CORP·Filed 2015·Granted Jun 19, 2018·2 cites·27 claims
- 1380US9596108B2Method and apparatus for baud-rate timing recoveryINTEL CORP·Filed 2014·Granted Mar 14, 2017·5 cites·19 claims
- 1478US2025225090A1High performance interconnectINTEL CORP·Filed 2025·Application pending·0 cites
- 1574US11269793B2High performance interconnectINTEL CORP·Filed 2020·Granted Mar 8, 2022·0 cites·21 claims
- 1671US2019391939A1High performance interconnectINTEL CORP·Filed 2019·Application pending·0 cites
- 1765US7382197B2Adaptive tuning circuit to maximize output signal amplitude for an amplifierINTEL CORP·Filed 2006·Granted Jun 3, 2008·5 cites·11 claims
- 1863US9965370B2Automated detection of high performance interconnect couplingINTEL CORP·Filed 2015·Granted May 8, 2018·1 cites·21 claims
- 1956US10069658B2Pulsed decision feedback equalization circuitINTEL CORP·Filed 2015·Granted Sep 4, 2018·1 cites·20 claims
- 2053US9048084B2Apparatus and method for extending bandwidth and supressing phase errors in multi-phase signalsINTEL CORP·Filed 2014·Granted Jun 2, 2015·0 cites·19 claims
- 2148US8031764B2Multiplexer based transmitter equalizationINTEL CORP·Filed 2008·Granted Oct 4, 2011·0 cites·18 claims
- 2242US8779823B2Apparatus and method for extending bandwidth and suppressing phase errors in multi-phase signalsIYER SITARAMAN V·Filed 2012·Granted Jul 15, 2014·0 cites·28 claims
- 2334US2009322389A1Jitter attenuating delay locked loop (dll) using a regenerative delay lineSINGH GUNEET·Filed 2008·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →