High performance interconnect

Abstract

A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state

What is claimed is: 
     
         1 . An apparatus comprising
 a physical layer (PHY) configured to be coupled to a serial, differential link that is to include a number of lanes, the PHY to include a transmitter and a receiver to be coupled to each lane of the number of lanes, wherein the transmitter to be coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and wherein the PHY is to periodically issue a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration, wherein the PHY is to utilize the serial, differential link during the duration for a PHY associated task selected from a group consisting of an in-band reset, an entry into low power state, and an entry into partial width state.   
     
     
         2 . An apparatus comprising:
 physical layer logic to:
 receive a training sequence, wherein at least a portion of the training sequence is to be scrambled through use of a pseudo random bit sequence (PRBS) and at least a header of the training sequence is to be unscrambled; and 
 perform adaptation of a link based at least in part on the scrambled portion of the training sequence. 
   
     
     
         3 . An apparatus comprising:
 link layer logic to generate a header flit that is to comprise at least three slots, wherein the header flit is to include at least 192 bits, a transaction identifier of at least 11 bits, a cyclical redundancy check field of at least 16 bits, and a floating field to expand any one of two or more of the three slots.