Inventor · disambiguated record
Herbert Hum
Also filed as: HUM HERBERT · HUM HERBERT H · HUM HERBERT H J · HUM HERBERT HING-JING
74 granted patents·8 pending applications·751 citations·filing 1997–2025
99Inventor score
Top patents by PatentIndex Score
82 records- 0196US12197357B2High performance interconnectINTEL CORP·Filed 2021·Granted Jan 14, 2025·2 cites·20 claims
- 0294US9626321B2High performance interconnectINTEL CORP·Filed 2013·Granted Apr 18, 2017·14 cites·1 claims
- 0394US8615647B2Migrating execution of thread between cores of different instruction set architecture in multi-core processor and transitioning each core to respective on / off power stateHUM HERBERT·Filed 2008·Granted Dec 24, 2013·34 cites·20 claims
- 0493US10248591B2High performance interconnectINTEL CORP·Filed 2016·Granted Apr 2, 2019·5 cites·23 claims
- 0593US9829965B2Distribution of tasks among asymmetric processing elementsINTEL CORP·Filed 2014·Granted Nov 28, 2017·11 cites·18 claims
- 0692US11741030B2High performance interconnectINTEL CORP·Filed 2020·Granted Aug 29, 2023·2 cites·20 claims
- 0791US7360033B2Hierarchical virtual model of a cache hierarchy in a multiprocessor systemINTEL CORP·Filed 2006·Granted Apr 15, 2008·22 cites·3 claims
- 0890US7269698B2Hierarchical virtual model of a cache hierarchy in a multiprocessor systemINTEL CORP·Filed 2005·Granted Sep 11, 2007·20 cites·24 claims
- 0990US2025321910A1High performance interconnectINTEL CORP·Filed 2025·Application pending·0 cites
- 1089US6922756B2Forward state for use in cache coherency in a multiprocessor systemINTEL CORP·Filed 2002·Granted Jul 26, 2005·57 cites·34 claims
- 1187US7095342B1Compressing microcodeINTEL CORP·Filed 2005·Granted Aug 22, 2006·19 cites·29 claims
- 1286US6798364B2Method and apparatus for variable length codingINTEL CORP·Filed 2002·Granted Sep 28, 2004·37 cites·30 claims
- 1385US12189550B2High performance interconnectINTEL CORP·Filed 2023·Granted Jan 7, 2025·0 cites·20 claims
- 1485US9753530B2Distribution of tasks among asymmetric processing elementsINTEL CORP·Filed 2014·Granted Sep 5, 2017·3 cites·6 claims
- 1585US7958336B2System and method for reservation station load dependency matrixINTEL CORP·Filed 2008·Granted Jun 7, 2011·17 cites·12 claims
- 1685US7434006B2Non-speculative distributed conflict resolution for a cache coherency protocolINTEL CORP·Filed 2005·Granted Oct 7, 2008·13 cites·18 claims
- 1783US8392665B2Allocation and write policy for a glueless area-efficient directory cache for hotly contested cache linesMOGA ADRIAN C·Filed 2010·Granted Mar 5, 2013·12 cites·30 claims
- 1883US6954829B2Non-speculative distributed conflict resolution for a cache coherency protocolINTEL CORP·Filed 2002·Granted Oct 11, 2005·31 cites·14 claims
- 1983US6922745B2Method and apparatus for handling locksINTEL CORP·Filed 2002·Granted Jul 26, 2005·42 cites·32 claims
- 2082US11054890B2Distribution of tasks among asymmetric processing elementsINTEL CORP·Filed 2013·Granted Jul 6, 2021·3 cites·18 claims
- 2182US9760162B2Distribution of tasks among asymmetric processing elementsINTEL CORP·Filed 2013·Granted Sep 12, 2017·3 cites·8 claims
- 2282US6675282B2System and method for employing a global bit for page sharing in a linear-addressed cacheINTEL CORP·Filed 2003·Granted Jan 6, 2004·29 cites·36 claims
- 2381US6643743B1Stream-down prefetching cacheINTEL CORP·Filed 2000·Granted Nov 4, 2003·26 cites·30 claims
- 2480US10725920B2Processors having virtually clustered cores and cache slicesINTEL CORP·Filed 2018·Granted Jul 28, 2020·2 cites·26 claims
- 2580US10705960B2Processors having virtually clustered cores and cache slicesINTEL CORP·Filed 2018·Granted Jul 7, 2020·2 cites·21 claims
- 2680US9170946B2Directory cache supporting non-atomic input/output operationsHUM HERBERT H·Filed 2012·Granted Oct 27, 2015·9 cites·16 claims
- 2780US7257693B2Multi-processor computing system that employs compressed cache lines' worth of information and processor capable of use in said systemINTEL CORP·Filed 2004·Granted Aug 14, 2007·28 cites·20 claims
- 2879US9874926B2Distribution of tasks among asymmetric processing elementsINTEL CORP·Filed 2014·Granted Jan 23, 2018·2 cites·12 claims
- 2978US9870046B2Distribution of tasks among asymmetric processing elementsINTEL CORP·Filed 2013·Granted Jan 16, 2018·2 cites·12 claims
- 3078US2025225090A1High performance interconnectINTEL CORP·Filed 2025·Application pending·0 cites
- 3175US10725919B2Processors having virtually clustered cores and cache slicesINTEL CORP·Filed 2018·Granted Jul 28, 2020·1 cites·22 claims
- 3275US9037903B2Apparatus and method for partial memory mirroringHUM HERBERT H·Filed 2012·Granted May 19, 2015·5 cites·20 claims
- 3375US7721050B2Re-snoop for conflict resolution in a cache coherency protocolINTEL CORP·Filed 2006·Granted May 18, 2010·8 cites·17 claims
- 3475US7643477B2Buffering data packets according to multiple flow control schemesINTEL CORP·Filed 2005·Granted Jan 5, 2010·6 cites·19 claims
- 3575US7111128B2Hierarchical virtual model of a cache hierarchy in a multiprocessor systemINTEL CORP·Filed 2002·Granted Sep 19, 2006·16 cites·5 claims
- 3674US11366511B2Distribution of tasks among asymmetric processing elementsINTEL CORP·Filed 2020·Granted Jun 21, 2022·0 cites·29 claims
- 3774US11269793B2High performance interconnectINTEL CORP·Filed 2020·Granted Mar 8, 2022·0 cites·21 claims
- 3874US8789031B2Software constructed strands for execution on a multi-core architectureLIU WEI·Filed 2007·Granted Jul 22, 2014·9 cites·9 claims
- 3974US8452946B2Methods and apparatuses for efficient load processing using buffersLIU WEI·Filed 2009·Granted May 28, 2013·5 cites·15 claims
- 4074US6078992ADirty line cacheINTEL CORP·Filed 1997·Granted Jun 20, 2000·69 cites·22 claims
- 4173US9910483B2Distribution of tasks among asymmetric processing elementsINTEL CORP·Filed 2014·Granted Mar 6, 2018·1 cites·4 claims
- 4273US7130969B2Hierarchical directories for cache coherency in a multiprocessor systemINTEL CORP·Filed 2002·Granted Oct 31, 2006·16 cites·43 claims
- 4372US9939882B2Systems and methods for migrating processes among asymmetrical processing coresINTEL CORP·Filed 2013·Granted Apr 10, 2018·1 cites·6 claims
- 4472US6954822B2Techniques to map cache data to memory arraysINTEL CORP·Filed 2002·Granted Oct 11, 2005·18 cites·24 claims
- 4571US7996572B2Multi-node chipset lock flow with peer-to-peer non-posted I/O requestsINTEL CORP·Filed 2004·Granted Aug 9, 2011·16 cites·30 claims
- 4671US2019391939A1High performance interconnectINTEL CORP·Filed 2019·Application pending·0 cites
- 4770US8171095B2Speculative distributed conflict resolution for a cache coherency protocolHUM HERBERT H J·Filed 2011·Granted May 1, 2012·4 cites·16 claims
- 4870US7512750B2Processor and memory controller capable of use in computing system that employs compressed cache lines' worth of informationINTEL CORP·Filed 2003·Granted Mar 31, 2009·15 cites·33 claims
- 4968US8151096B2Method to improve branch prediction latencyHUM HERBERT·Filed 2008·Granted Apr 3, 2012·5 cites·23 claims
- 5068US7716409B2Globally unique transaction identifiersINTEL CORP·Filed 2004·Granted May 11, 2010·11 cites·22 claims
Showing the top 50 of 82 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →